Module Name:	pkgsrc
Committed By:	drochner
Date:		Thu May  4 16:58:05 UTC 2006

Modified Files:
	pkgsrc/cad/MyHDL-gplcver: Makefile distinfo
	pkgsrc/cad/MyHDL-gplcver/patches: patch-aa
	pkgsrc/cad/MyHDL-iverilog: Makefile distinfo
	pkgsrc/cad/py-MyHDL: Makefile PLIST distinfo

Log Message:
update MyHDL to 0.5.1
There is no usable changelog; I've found one real bug closed in the
tracker: A verilog '>>>' is generated as appropriate for signed numbers.


To generate a diff of this commit:
cvs rdiff -r1.2 -r1.3 pkgsrc/cad/MyHDL-gplcver/Makefile
cvs rdiff -r1.1.1.1 -r1.2 pkgsrc/cad/MyHDL-gplcver/distinfo
cvs rdiff -r1.1.1.1 -r1.2 pkgsrc/cad/MyHDL-gplcver/patches/patch-aa
cvs rdiff -r1.2 -r1.3 pkgsrc/cad/MyHDL-iverilog/Makefile
cvs rdiff -r1.1.1.1 -r1.2 pkgsrc/cad/MyHDL-iverilog/distinfo
cvs rdiff -r1.12 -r1.13 pkgsrc/cad/py-MyHDL/Makefile
cvs rdiff -r1.4 -r1.5 pkgsrc/cad/py-MyHDL/PLIST pkgsrc/cad/py-MyHDL/distinfo

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.