Module Name:	pkgsrc
Committed By:	drochner
Date:		Fri Feb 10 16:06:46 UTC 2006

Modified Files:
	pkgsrc/cad/py-MyHDL: Makefile PLIST distinfo

Log Message:
update to 0.5
major changes:
-supports Python decorator syntax for generators (needs 2.4)
-intbv() doesn't have a default anymore
-many improvements to Verilog conversion


To generate a diff of this commit:
cvs rdiff -r1.10 -r1.11 pkgsrc/cad/py-MyHDL/Makefile
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/py-MyHDL/PLIST pkgsrc/cad/py-MyHDL/distinfo

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.