Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Sun Dec 15 01:57:12 UTC 2002

Modified Files:
	pkgsrc/cad/verilog: Makefile PLIST distinfo

Log Message:
update to verilog-0.7

This release represents many bug fixes, expanded language coverage,
greatly enhanced xilinx fpga synthesis and several performance enhancements.
The complete list is rather long.


To generate a diff of this commit:
cvs rdiff -r1.12 -r1.13 pkgsrc/cad/verilog/Makefile
cvs rdiff -r1.2 -r1.3 pkgsrc/cad/verilog/PLIST
cvs rdiff -r1.4 -r1.5 pkgsrc/cad/verilog/distinfo

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.