Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Sat Dec 15 18:43:38 UTC 2001

Modified Files:
	pkgsrc/cad/verilog-current: Makefile distinfo

Log Message:
update to verilog-current-20011209 snapshot.

Many changes since the last packaged snapshot.  A sampling of these are:

Support for hierarchical names has been largely rewritten. The major
consequence of this is that escaped names now have much better
support. By now, most any combination of escaped and hierarchical name
should work properly, for nets, parameters, and anything else.

Output delays for primitive gates, including user defined primitivies,
should now work properly. Delays on nets still do not work, although
the parser now parses them and prints a "sorry" message.

Bugs in support for division(/) and modulus (%) have been fixed.

Bugs in l-values of synthesized DFF devices have been fixed. These
bugs were related to part selects of vectors in l-values.

A few XNF code generator bugs and limitations were fixed.

And as usual, a variety of miscellaneous bugs have been fixed in this
snapshot.

The bit size of the results of some unary redunction operators is now
properly handled. Also, similar problems with logical functions have
been fixed.

force/release now works for variables, though not yet for
nets. Assign/deassign already work.

many other bugfixes


To generate a diff of this commit:
cvs rdiff -r1.22 -r1.23 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.6 -r1.7 pkgsrc/cad/verilog-current/distinfo

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.