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[pkgsrc/trunk]: pkgsrc/cross/xtensa-lx106-elf-binutils Add xtensa-lx106-elf-b...
details: https://anonhg.NetBSD.org/pkgsrc/rev/85e60275e6a3
branches: trunk
changeset: 340000:85e60275e6a3
user: bouyer <bouyer%pkgsrc.org@localhost>
date: Fri Sep 20 15:18:59 2019 +0000
description:
Add xtensa-lx106-elf-binutils version 2.31_20190405. Build options taken
from https://github.com/earlephilhower/esp-quick-toolchain.
This is a version compatible with the Arduino environement.
Cross binutils for chips using the Xtensa lx106 core, such as the
Espressif ESP8266 wireless modules.
diffstat:
cross/xtensa-lx106-elf-binutils/DESCR | 2 +
cross/xtensa-lx106-elf-binutils/Makefile | 35 +
cross/xtensa-lx106-elf-binutils/PLIST | 72 +
cross/xtensa-lx106-elf-binutils/distinfo | 6 +
cross/xtensa-lx106-elf-binutils/files/xtensa-config.h | 715 ++++++++++++++++++
5 files changed, 830 insertions(+), 0 deletions(-)
diffs (truncated from 850 to 300 lines):
diff -r cc150060e5cd -r 85e60275e6a3 cross/xtensa-lx106-elf-binutils/DESCR
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cross/xtensa-lx106-elf-binutils/DESCR Fri Sep 20 15:18:59 2019 +0000
@@ -0,0 +1,2 @@
+Cross binutils for chips using the Xtensa lx106 core, such as the
+Espressif ESP8266 wireless modules.
diff -r cc150060e5cd -r 85e60275e6a3 cross/xtensa-lx106-elf-binutils/Makefile
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cross/xtensa-lx106-elf-binutils/Makefile Fri Sep 20 15:18:59 2019 +0000
@@ -0,0 +1,35 @@
+# $NetBSD: Makefile,v 1.1 2019/09/20 15:18:59 bouyer Exp $
+
+DISTNAME= binutils-gdb-xtensa-2.31_20190405
+PKGNAME= ${DISTNAME:C/binutils-gdb-xtensa/xtensa-lx106-elf-binutils/}
+CATEGORIES= cross
+MASTER_SITES= ${MASTER_SITE_GITHUB:=jcmvbkbc/}
+GITHUB_PROJECT= binutils-gdb-xtensa
+GITHUB_TAG= c0b4cd465573f1772927cb3ad5d6e7d17af21622
+
+MAINTAINER= bouyer%NetBSD.org@localhost
+HOMEPAGE= https://github.com/espressif/binutils-gdb
+COMMENT= Cross binutils for Espressif ESP8266 bare metal environment
+LICENSE= gnu-gpl-v2 AND gnu-gpl-v3 AND gnu-lgpl-v2 AND gnu-lgpl-v3
+
+INFO_FILES= yes
+GNU_CONFIGURE= yes
+USE_LIBTOOL= yes
+USE_TOOLS+= gmake makeinfo perl
+
+OBJDIR= ../build
+CONFIGURE_DIRS= ${OBJDIR}
+CONFIGURE_SCRIPT= ${WRKSRC}/configure
+GNU_CONFIGURE_PREFIX= ${PREFIX}/xtensa-lx106-elf
+
+CONFIGURE_ARGS+= --disable-werror
+CONFIGURE_ARGS+= --target=xtensa-lx106-elf
+CONFIGURE_ARGS+= --enable-multilib
+CONFIGURE_ARGS+= --disable-nls
+CONFIGURE_ARGS+= --disable-gdb
+
+pre-configure:
+ ${RUN} cd ${WRKSRC} && ${MKDIR} ${OBJDIR}
+ ${CP} ${FILESDIR}/xtensa-config.h ${WRKSRC}/include/xtensa-config.h
+
+.include "../../mk/bsd.pkg.mk"
diff -r cc150060e5cd -r 85e60275e6a3 cross/xtensa-lx106-elf-binutils/PLIST
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cross/xtensa-lx106-elf-binutils/PLIST Fri Sep 20 15:18:59 2019 +0000
@@ -0,0 +1,72 @@
+@comment $NetBSD: PLIST,v 1.1 2019/09/20 15:18:59 bouyer Exp $
+xtensa-lx106-elf/bin/xtensa-lx106-elf-addr2line
+xtensa-lx106-elf/bin/xtensa-lx106-elf-ar
+xtensa-lx106-elf/bin/xtensa-lx106-elf-as
+xtensa-lx106-elf/bin/xtensa-lx106-elf-c++filt
+xtensa-lx106-elf/bin/xtensa-lx106-elf-elfedit
+xtensa-lx106-elf/bin/xtensa-lx106-elf-gprof
+xtensa-lx106-elf/bin/xtensa-lx106-elf-ld
+xtensa-lx106-elf/bin/xtensa-lx106-elf-ld.bfd
+xtensa-lx106-elf/bin/xtensa-lx106-elf-nm
+xtensa-lx106-elf/bin/xtensa-lx106-elf-objcopy
+xtensa-lx106-elf/bin/xtensa-lx106-elf-objdump
+xtensa-lx106-elf/bin/xtensa-lx106-elf-ranlib
+xtensa-lx106-elf/bin/xtensa-lx106-elf-readelf
+xtensa-lx106-elf/bin/xtensa-lx106-elf-size
+xtensa-lx106-elf/bin/xtensa-lx106-elf-strings
+xtensa-lx106-elf/bin/xtensa-lx106-elf-strip
+xtensa-lx106-elf/info/as.info
+xtensa-lx106-elf/info/bfd.info
+xtensa-lx106-elf/info/binutils.info
+xtensa-lx106-elf/info/gprof.info
+xtensa-lx106-elf/info/ld.info
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-addr2line.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-ar.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-as.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-c++filt.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-dlltool.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-elfedit.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-gprof.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-ld.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-nm.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-objcopy.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-objdump.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-ranlib.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-readelf.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-size.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-strings.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-strip.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-windmc.1
+xtensa-lx106-elf/man/man1/xtensa-lx106-elf-windres.1
+xtensa-lx106-elf/xtensa-lx106-elf/bin/ar
+xtensa-lx106-elf/xtensa-lx106-elf/bin/as
+xtensa-lx106-elf/xtensa-lx106-elf/bin/ld
+xtensa-lx106-elf/xtensa-lx106-elf/bin/ld.bfd
+xtensa-lx106-elf/xtensa-lx106-elf/bin/nm
+xtensa-lx106-elf/xtensa-lx106-elf/bin/objcopy
+xtensa-lx106-elf/xtensa-lx106-elf/bin/objdump
+xtensa-lx106-elf/xtensa-lx106-elf/bin/ranlib
+xtensa-lx106-elf/xtensa-lx106-elf/bin/readelf
+xtensa-lx106-elf/xtensa-lx106-elf/bin/strip
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.x
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xbn
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xc
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xce
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xd
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xdc
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xdce
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xde
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xdw
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xdwe
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xe
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xn
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xr
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xs
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xsc
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xsce
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xse
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xsw
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xswe
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xu
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xw
+xtensa-lx106-elf/xtensa-lx106-elf/lib/ldscripts/elf32xtensa.xwe
diff -r cc150060e5cd -r 85e60275e6a3 cross/xtensa-lx106-elf-binutils/distinfo
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cross/xtensa-lx106-elf-binutils/distinfo Fri Sep 20 15:18:59 2019 +0000
@@ -0,0 +1,6 @@
+$NetBSD: distinfo,v 1.1 2019/09/20 15:18:59 bouyer Exp $
+
+SHA1 (binutils-gdb-xtensa-2.31_20190405-c0b4cd465573f1772927cb3ad5d6e7d17af21622.tar.gz) = 6e7e15f6cbcff5e7e02b2a757b859b3104b1cdd2
+RMD160 (binutils-gdb-xtensa-2.31_20190405-c0b4cd465573f1772927cb3ad5d6e7d17af21622.tar.gz) = 7e604d7db91309a40c77b2d8139d9d9db58bb753
+SHA512 (binutils-gdb-xtensa-2.31_20190405-c0b4cd465573f1772927cb3ad5d6e7d17af21622.tar.gz) =
1394cd8d50b13b801caba4c44e51b0a2b31332d77d87456e89efc120e8bc7c3f7b34e42aa921efc845045ab591b4e1f9ce954334f3242f6ade6a30a539d5ef38
+Size (binutils-gdb-xtensa-2.31_20190405-c0b4cd465573f1772927cb3ad5d6e7d17af21622.tar.gz) = 57031990 bytes
diff -r cc150060e5cd -r 85e60275e6a3 cross/xtensa-lx106-elf-binutils/files/xtensa-config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cross/xtensa-lx106-elf-binutils/files/xtensa-config.h Fri Sep 20 15:18:59 2019 +0000
@@ -0,0 +1,715 @@
+/*
+ * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
+ * processor CORE configuration
+ *
+ * See <xtensa/config/core.h>, which includes this file, for more details.
+ */
+
+/* Xtensa processor core configuration information.
+
+ Copyright (c) 1999-2010 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+
+/****************************************************************************
+ Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ * configured, and a value of 0 otherwise. These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+ ISA
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED 0 /* windowed registers option */
+#define XCHAL_NUM_AREGS 16 /* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2 4 /* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG 1 /* debug option */
+#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
+#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX 0 /* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT 0 /* SEXT instruction */
+#define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R 1 /* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
+#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12 0 /* (obsolete option) */
+#define XCHAL_HAVE_ABS 1 /* ABS instruction */
+/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
+/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION 0 /* speculation */
+#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS 1 /* */
+#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID 1 /* processor ID register */
+#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
+#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
+#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
+#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
+#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
+#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
+#define XCHAL_HAVE_FP 0 /* floating point pkg */
+#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
+#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
+#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
+#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
+#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
+
+
+/*----------------------------------------------------------------------
+ MISC
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES 1 /* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
+/* In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
+#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
+#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
+
+#define XCHAL_SW_VERSION 800001 /* sw version of this header */
+
+#define XCHAL_CORE_ID "lx106" /* alphanum core name
+ (CoreID) set in the Xtensa
+ Processor Generator */
+
+#define XCHAL_BUILD_UNIQUE_ID 0x0002B6F6 /* 22-bit sw build ID */
+
+/*
+ * These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0 0xC28CDAFA /* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1 0x1082B6F6 /* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME "LX3.0.1" /* full version name */
+#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION 230001 /* major*100+minor */
+#define XCHAL_HW_REL_LX3 1
+#define XCHAL_HW_REL_LX3_0 1
+#define XCHAL_HW_REL_LX3_0_1 1
+#define XCHAL_HW_CONFIGID_RELIABLE 1
+/* If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION 230001 /* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION 230001 /* latest targeted hw */
+
+
+/*----------------------------------------------------------------------
+ CACHE
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
+#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
+
+#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
+
+
+
+
+/****************************************************************************
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