> Mipam wrote:
> > Hi,
> > 
> > I bought two intel 82541 GI NIC's, but i noticed 1.6 doesnt support them.
> > Are they supported in current or will they be supported in 2.0?
> > 
> > In dmesg this shows up for the two cards.
> > 
> > Intel product 0x1076 (ethernet network) at pci0 dev 10 function 0 not 
> > configured
> > Intel product 0x1076 (ethernet network) at pci0 dev 13 function 0 not 
> > configured

Hnmm, i checked and there is no support for it in 1.6 yet.
In current it seems to be there.
Suppose i would add underneath changes to the files listed below in 
1.6 (from 
current sources) would this card work?

src/sys/dev/pci/pcidevs 
product INTEL 82541GI           0x1076  i82541GI Gigabit Ethernet

sys/dev/pci/pcidevs.h
#define PCI_PRODUCT_INTEL_82541GI       0x1076          /* i82541GI 
Gigabit Ethernet */

sys/dev/pci/pcidevs_data.h
{ 
               PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 
               0, 
               "Intel", 
               "i82541GI Gigabit Ethernet", 
           }, 

sys/dev/pci/if_wm.c
{ PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82541GI, 
             "Intel i82541GI 1000BASE-T Ethernet", 
             WM_T_82541_2,         WMP_F_1000T }, 


 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);          switch (sc->sc_type) { 
           case WM_T_82544: 
           case WM_T_82540: 
           case WM_T_82545: 
           case WM_T_82546: 
           case WM_T_82541: 
           case WM_T_82541_2: 
                   /* 
                    * These chips have a problem with the memory-mapped 
                    * write cycle when issuing the reset, so use 
I/O-mapped 
                    * access, if possible. 
                    */ 
                   if (sc->sc_flags & WM_F_IOH_VALID) 
                           wm_io_write(sc, WMREG_CTRL, CTRL_RST); 
                   else 
                           CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 
                   break; 
    
           case WM_T_82545_3: 
           case WM_T_82546_3: 
                   /* Use the shadow control register on these chips. */ 
                   CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 
                   break; 
    
           default: 
                   /* Everything else can safely use the documented 
method. */ 
                   CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 
                   break; 
           } 


typedef enum { 
           WM_T_unknown            = 0, 
           WM_T_82542_2_0,                 /* i82542 2.0 (really old) */ 
           WM_T_82542_2_1,                 /* i82542 2.1+ (old) */ 
           WM_T_82543,                     /* i82543 */ 
           WM_T_82544,                     /* i82544 */ 
           WM_T_82540,                     /* i82540 */ 
           WM_T_82545,                     /* i82545 */ 
           WM_T_82545_3,                   /* i82545 3.0+ */ 
           WM_T_82546,                     /* i82546 */ 
           WM_T_82546_3,                   /* i82546 3.0+ */ 
           WM_T_82541,                     /* i82541 */ 
           WM_T_82541_2,                   /* i82541 2.0+ */ 
           WM_T_82547,                     /* i82547 */ 
           WM_T_82547_2,                   /* i82547 2.0+ */ 
   } wm_chip_type; 

Bye,

Mipam.