PR/60664 CVS commit: src/sys/arch/mips/mips

["Nick Hudson" <skrll%netbsd.org@localhost>]

The following reply was made to PR port-mips/60664; it has been noted by GNATS.

From: "Nick Hudson" <skrll%netbsd.org@localhost>
To: gnats-bugs%gnats.NetBSD.org@localhost
Cc: 
Subject: PR/60664 CVS commit: src/sys/arch/mips/mips
Date: Fri, 25 Sep 2026 16:30:31 +0000

 Module Name:	src
 Committed By:	skrll
 Date:		Fri Sep 25 16:30:31 UTC 2026
 
 Modified Files:
 	src/sys/arch/mips/mips: mipsX_subr.S
 
 Log Message:
 mips: fix rdhwr emulation wrt TLB misses on loading the faulting instruction.
 
 Use tlbp to probe the TLB for an entry for the page containing the
 instruction to emulate, and fail to slow path if it doesn't exist.
 
 A TLB miss (nested exception) on the instruction load would otherwise
 land in user_gen_exception and clobber this routine's v0, since the
 exception PC isn't saved again while EXL is set.
 
 PR/60664 mips: rdhwr emulation corrupts v0 on nested TLB miss...
 
 This patch is based on the diff included in the PR, but updated by me
 to improve register save / restore in both the fast and slow paths.
 
 The mf* instructions in user_gen_exception_common are shuffled down
 to maintain the same number of stores (4) between each mf* in
 user_gen_exception_common and user_gen_exception_common2
 
 The symptoms that this change fixes match those described in
 
 port-evbmips/59236: Multiple segfaults in erlite3 boot
 
 
 To generate a diff of this commit:
 cvs rdiff -u -r1.118 -r1.119 src/sys/arch/mips/mips/mipsX_subr.S
 
 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.