PR/59653 CVS commit: [netbsd-11] src/sys/arch/riscv/riscv

["Martin Husemann" <martin%netbsd.org@localhost>]

The following reply was made to PR port-riscv/59653; it has been noted by GNATS.

From: "Martin Husemann" <martin%netbsd.org@localhost>
To: gnats-bugs%gnats.NetBSD.org@localhost
Cc: 
Subject: PR/59653 CVS commit: [netbsd-11] src/sys/arch/riscv/riscv
Date: Wed, 1 Oct 2025 16:37:05 +0000

 Module Name:	src
 Committed By:	martin
 Date:		Wed Oct  1 16:37:05 UTC 2025
 
 Modified Files:
 	src/sys/arch/riscv/riscv [netbsd-11]: bus_dma.c
 
 Log Message:
 Pull up following revision(s) (requested by skrll in ticket #38):
 
 	sys/arch/riscv/riscv/bus_dma.c: revision 1.11
 
 risc-v: Adjust barriers issued in bus_dmamap_sync for the coherent case.
 PR/59653
 
 This change adjusts the memory barriers issued by bus_dmamap_sync for
 the coherent case. In the non-coherent case the CPU cache operations
 are expected to provide any, and all required barriers.
 These barriers are emitted after bouncing for PREWRITE and before
 bouncing for POSTREAD.
 
 Net change:
 op                      old                     new
 ---------------------   ----------------------  --------------
 PREREAD                 none                    fence rw,ow
 PREWRITE                fence iorw,iorw         fence rw,ow
 PREREAD|PREWRITE        fence iorw,iorw         fence w,ow
 POSTREAD                fence iorw,iorw         fence ir,r
 POSTWRITE               none                    none
 POSTREAD|POSTWRITE      fence iorw,iorw         fence ir,r
 
 
 To generate a diff of this commit:
 cvs rdiff -u -r1.10 -r1.10.2.1 src/sys/arch/riscv/riscv/bus_dma.c
 
 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.