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lib/58253: powerpc has more fenv exception bits than it can handle
>Number: 58253
>Category: lib
>Synopsis: powerpc has more fenv exception bits than it can handle
>Confidential: no
>Severity: serious
>Priority: medium
>Responsible: lib-bug-people
>State: open
>Class: sw-bug
>Submitter-Id: net
>Arrival-Date: Sun May 12 21:45:00 +0000 2024
>Originator: Taylor R Campbell
>Release: current, 10, 9, ...
>Organization:
The NetBSFE_ALL_FOUNDATION
>Environment:
>Description:
The PowerPC architecture supports a large set of sticky exception bits, but a small set of exception trap-enable bits -- aside from the five standard IEEE 754 sticky exception bits (invalid-operation, inexact-result, divide-by-zero, overflow, underflow), there are fine-grained invalid-operation bits like SNaN input, infinity minus infinity, infinity divided by infinity, zero divided by zero, and so on.
Reference: PowerPC User Instruction Set Architecture, Book I, Version 2.02, January 28, 2005, Sec. 4.2.2 Floating-Point Status and Control Register, pp. 87-89.
http://public.dhe.ibm.com/software/dw/library/es-ppcbook1.zip
The fine-grained invalid-operation exception bits are included in FE_ALL_EXCEPT, and you can test the them with, e.g., fetestexcept(FE_VXSNAN) (SNaN input). You can also enable trapping on the standard IEEE 754 exception bits, like feenableexcept(FE_INVALID).
But there are no architectural bits for trapping the fine-grained invalid-operation exception bits.
Currently feenableexcept simply ignores any fine-grained invalid-operation exception bits, which has the effect that after feenableexcept(FE_ALL_EXCEPT), fegetexcept() doesn't return FE_ALL_EXCEPT -- it just returns FE_DIVBYZERO|FE_INEXACT|FE_INVALID|FE_OVERFLOW|FE_UNDERFLOW:
https://releng.netbsd.org/b5reports/macppc/2024/2024.05.11.22.29.36/test.html#lib_libm_t_fenv_fetestexcept_trap
>How-To-Repeat:
#include <fenv.h>
feenableexcept(FE_ALL_EXCEPT);
if (fegetexcept() != FE_ALL_EXCEPT)
abort();
>Fix:
Yes, please!
Maybe we should define FE_TRAP_EXCEPT (under _NETBSD_SOURCE, since it's nonstandard):
- On powerpc, this would be FE_DIVBYZERO|FE_INEXACT|FE_INVALID|FE_OVERFLOW|FE_UNDERFLOW.
- On architectures where all exceptions in FE_ALL_EXCEPT can be trapped, this would be the same as FE_ALL_EXCEPT.
- On architectures that don't architecturally support trapping exceptions, even in principle, like riscv which has no bits for requesting traps, this could be zero.
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