Re: port-evbarm/56420: panic: kernel diagnostic assertion "ipl > ci->ci_cpl" failed:

[Nick Hudson <nick.hudson%gmx.co.uk@localhost>]

On 29/09/2021 06:50, mac%culver.net@localhost wrote:
> > Number:         56420
> > Category:       port-evbarm
> > Synopsis:       when system is idle,  panic: kernel diagnostic assertion "ipl > ci->ci_cpl" failed: file "/src/sys/arch/arm/cortex/gic.c", line 381 ipl 7 cpl 7 hw-ipl 0x90

Please try this patch

Thanks,
Nick

Index: sys/arch/arm/cortex/gic.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/cortex/gic.c,v
retrieving revision 1.50
diff -u -p -r1.50 gic.c
--- sys/arch/arm/cortex/gic.c	26 Sep 2021 13:38:50 -0000	1.50
+++ sys/arch/arm/cortex/gic.c	2 Oct 2021 20:57:52 -0000
@@ -331,9 +331,17 @@ armgic_irq_handler(void *tf)

 	ci->ci_data.cpu_nintr++;

-	if (ci->ci_hwpl != old_ipl) {
+	/*
+	 * Raise ci_hwpl (and PMR) to ci_cpl and IAR will tell us if the
+	 * interrupt that got us here can have its handler run or not.
+	 */
+	if (ci->ci_hwpl <= old_ipl) {
 		ci->ci_hwpl = old_ipl;
 		gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(old_ipl));
+		/*
+		 * we'll get no interrupts when PMR is IPL_HIGH, so bail
+		 * early.
+		 */
 		if (old_ipl == IPL_HIGH) {
 			return;
 		}
@@ -373,11 +381,13 @@ armgic_irq_handler(void *tf)
 		 *
 		 * However, if are just raising ipl, we can just update ci_cpl.
 		 */
+
+		/* Surely we can KASSERT(ipl < ci->ci_cpl); */
 		const int ipl = is->is_ipl;
 		if (__predict_false(ipl < ci->ci_cpl)) {
 			pic_do_pending_ints(I32_bit, ipl, tf);
 			KASSERT(ci->ci_cpl == ipl);
-		} else {
+		} else if (ci->ci_cpl != ipl) {
 			KASSERTMSG(ipl > ci->ci_cpl, "ipl %d cpl %d hw-ipl %#x",
 			    ipl, ci->ci_cpl,
 			    gicc_read(sc, GICC_PMR));