Re: port-i386/53494: vte doesn't work on eBox 3352DX3-AP

[Andrius V <vezhlys%gmail.com@localhost>]

The following reply was made to PR port-i386/53494; it has been noted by GNATS.

From: Andrius V <vezhlys%gmail.com@localhost>
To: gnats-bugs%netbsd.org@localhost
Cc: port-i386-maintainer%netbsd.org@localhost, gnats-admin%netbsd.org@localhost, 
	netbsd-bugs%netbsd.org@localhost
Subject: Re: port-i386/53494: vte doesn't work on eBox 3352DX3-AP
Date: Sun, 29 Aug 2021 02:10:38 +0300

 I reopened the bug, since I finally found what was causing the issue
 and it is not because of broken hardware. It appeared that after
 vte_reset VTE_MDCSC (MDC speed control) register value is set to
 default value 0x0030 instead of original 0x0068 value. This value
 controls clock speed from MAC to PHY (per my understanding) which
 explains why every second register fails to be read. Restoring value
 to original after reset solves the issue. Though for most this value
 is apparently default (including my own DX2, EX2 based systems), if
 somebody else can also test the patch and confirm that your system is
 not broken, it would be much appreciated. I tested my own systems,
 they seem to work. For DX3 you may need to boot without ACPI/SMP
 support (at least in my case).
 
 Patch can be downloaded here:
 https://ftp.netbsd.org/pub/NetBSD/misc/andvar/if_vte.c.diff
 
 Index: sys/dev/pci/if_vte.c
 ===================================================================
 RCS file: /cvsroot/src/sys/dev/pci/if_vte.c,v
 retrieving revision 1.31
 diff -u -p -r1.31 if_vte.c
 --- sys/dev/pci/if_vte.c    7 Feb 2020 00:04:28 -0000    1.31
 +++ sys/dev/pci/if_vte.c    28 Aug 2021 22:19:40 -0000
 @@ -1211,9 +1211,10 @@ vte_tick(void *arg)
  static void
  vte_reset(struct vte_softc *sc)
  {
 -    uint16_t mcr;
 +    uint16_t mcr, mdcsc;
      int i;
 
 +    mdcsc = CSR_READ_2(sc, VTE_MDCSC);
      mcr = CSR_READ_2(sc, VTE_MCR1);
      CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
      for (i = VTE_RESET_TIMEOUT; i > 0; i--) {
 @@ -1231,6 +1232,14 @@ vte_reset(struct vte_softc *sc)
      CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
      CSR_WRITE_2(sc, VTE_MACSM, 0);
      DELAY(5000);
 +
 +    /*
 +     * On some SoCs (like Vortex86DX3) MDC speed control register value needs
 +     * to be restored to original value instead of default one, otherwise
 +     * some PHY registers may fail to be read.
 +     */
 +    if (mdcsc != MDCSC_DEFAULT)
 +        CSR_WRITE_2(sc, VTE_MDCSC, mdcsc);
  }
 
 Regards,
 Andrius V
 
 On Sat, Jun 19, 2021 at 11:40 PM David Holland <dholland-bugs%netbsd.org@localhost> wrote:
 >
 > The following reply was made to PR port-i386/53494; it has been noted by GNATS.
 >
 > From: David Holland <dholland-bugs%netbsd.org@localhost>
 > To: gnats-bugs%netbsd.org@localhost
 > Cc: port-i386-maintainer%netbsd.org@localhost, gnats-admin%netbsd.org@localhost,
 >         netbsd-bugs%netbsd.org@localhost, vezhlys%gmail.com@localhost
 > Subject: Re: port-i386/53494: vte doesn't work on eBox 3352DX3-AP
 > Date: Sat, 19 Jun 2021 20:39:51 +0000
 >
 >  On Sat, Jun 19, 2021 at 08:30:03PM +0000, Andrius V wrote:
 >   >  However, I believe it just easier to consider my
 >   >  device broken and close the PR. In case I would somehow find a way to
 >   >  restore functionality programmatically (quite unlikely), I would
 >   >  create a patch for that.
 >
 >  Well, it's your device. I guess I'll close the PR but feel free to
 >  revisit it if you choose :-)
 >
 >  --
 >  David A. Holland
 >  dholland%netbsd.org@localhost
 >