NetBSD-Bugs archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
Re: kern/54592: uhub error when nvme is using msi(x) interrupts
The following reply was made to PR kern/54592; it has been noted by GNATS.
From: Thomas Klausner <wiz%NetBSD.org@localhost>
To: NetBSD bugtracking <gnats-bugs%NetBSD.org@localhost>
Cc:
Subject: Re: kern/54592: uhub error when nvme is using msi(x) interrupts
Date: Wed, 2 Oct 2019 13:18:29 +0200
intrctl list/vmstat -vi show the xhci entries though:
$ intrctl list
interrupt id CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11 CPU12 CPU13 CPU14 CPU15 CPU16 CPU17 CPU18 CPU19 CPU20 CPU21 CPU22 CPU23 CPU24 CPU25 CPU26 CPU27 CPU28 CPU29 CPU30 CPU31 device name(s)
ioapic0 pin 9 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 acpi SCI
msix0 vec 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 xhci0
msi1 vec 0 93* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ahcisata0
msix2 vec 0 0 44* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wm0TXRX0
msix2 vec 1 0 0 142* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wm0TXRX1
msix2 vec 2 1* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wm0LINK
msix3 vec 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 adminq
msix3 vec 1 1158* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq1
msix3 vec 2 0 693* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq2
msix3 vec 3 0 0 22* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq3
msix3 vec 4 0 0 0 12* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq4
msix3 vec 5 0 0 0 0 27* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq5
msix3 vec 6 0 0 0 0 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq6
msix3 vec 7 0 0 0 0 0 0 159* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq7
msix3 vec 8 0 0 0 0 0 0 0 48* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq8
msix3 vec 9 0 0 0 0 0 0 0 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq9
msix3 vec 10 0 0 0 0 0 0 0 0 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq10
msix3 vec 11 0 0 0 0 0 0 0 0 0 0 4* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq11
msix3 vec 12 0 0 0 0 0 0 0 0 0 0 0 160* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq12
msix3 vec 13 0 0 0 0 0 0 0 0 0 0 0 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq13
msix3 vec 14 0 0 0 0 0 0 0 0 0 0 0 0 0 391* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq14
msix3 vec 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq15
msix3 vec 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq16
msix3 vec 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 337* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq17
msix3 vec 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 121* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq18
msix3 vec 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq19
msix3 vec 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq20
msix3 vec 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0* 0 0 0 0 0 0 0 0 0 0 0 nvme0 ioq21
msix3 vec 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11* 0 0 0 0 0 0 0 0 0 0 nvme0 ioq22
msix3 vec 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 94* 0 0 0 0 0 0 0 0 0 nvme0 ioq23
msix3 vec 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25* 0 0 0 0 0 0 0 0 nvme0 ioq24
msix3 vec 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0* 0 0 0 0 0 0 0 nvme0 ioq25
msix3 vec 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0* 0 0 0 0 0 0 nvme0 ioq26
msix3 vec 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8* 0 0 0 0 0 nvme0 ioq27
msix3 vec 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0* 0 0 0 0 nvme0 ioq28
msix3 vec 29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0* 0 0 0 nvme0 ioq29
msix3 vec 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4* 0 0 nvme0 ioq30
msix3 vec 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 205* 0 nvme0 ioq31
msix3 vec 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2* nvme0 ioq32
msix4 vec 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 xhci1
msi5 vec 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ahcisata1
msi6 vec 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hdaudio0
msi7 vec 0 1* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hdaudio1
msix8 vec 0 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 xhci2
msi9 vec 0 0 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ahcisata2
ioapic2 pin 0 1343* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nouveau0
$ vmstat -v -i
interrupt total rate
TLB shootdown 3058 41
cpu0 timer 7236 97
ioapic0 pin 9 0 0
msix0 vec 0 0 0
msi1 vec 0 93 1
msix2 vec 0 51 0
msix2 vec 1 188 2
msix2 vec 2 1 0
msix3 vec 0 0 0
msix3 vec 1 1158 15
msix3 vec 2 693 9
msix3 vec 3 120 1
msix3 vec 4 12 0
msix3 vec 5 31 0
msix3 vec 6 0 0
msix3 vec 7 159 2
msix3 vec 8 48 0
msix3 vec 9 0 0
msix3 vec 10 0 0
msix3 vec 11 4 0
msix3 vec 12 160 2
msix3 vec 13 0 0
msix3 vec 14 391 5
msix3 vec 15 2 0
msix3 vec 16 18 0
msix3 vec 17 337 4
msix3 vec 18 121 1
msix3 vec 19 0 0
msix3 vec 20 0 0
msix3 vec 21 0 0
msix3 vec 22 11 0
msix3 vec 23 94 1
msix3 vec 24 25 0
msix3 vec 25 0 0
msix3 vec 26 0 0
msix3 vec 27 8 0
msix3 vec 28 0 0
msix3 vec 29 0 0
msix3 vec 30 4 0
msix3 vec 31 205 2
msix3 vec 32 2 0
msix4 vec 0 0 0
msi5 vec 0 0 0
msi6 vec 0 0 0
msi7 vec 0 1 0
msix8 vec 0 0 0
msi9 vec 0 0 0
ioapic2 pin 0 3449 46
Total 17680 238
Home |
Main Index |
Thread Index |
Old Index