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Re: kern/52818: The wm driver stops working after large traffic
The following reply was made to PR kern/52818; it has been noted by GNATS.
From: Masanobu SAITOH <msaitoh%execsw.org@localhost>
To: gnats-bugs%NetBSD.org@localhost, kern-bug-people%netbsd.org@localhost,
gnats-admin%netbsd.org@localhost, netbsd-bugs%netbsd.org@localhost, clare%csel.org@localhost
Cc: msaitoh%execsw.org@localhost
Subject: Re: kern/52818: The wm driver stops working after large traffic
Date: Thu, 28 Dec 2017 21:07:36 +0900
Hi.
On 2017/12/21 1:25, Shinichi Doyashiki wrote:
> The following reply was made to PR kern/52818; it has been noted by GNATS.
>
> From: Shinichi Doyashiki <clare%csel.org@localhost>
> To: gnats-bugs%NetBSD.org@localhost
> Cc: Hisashi T Fujinaka <htodd%twofifty.com@localhost>
> Subject: Re: kern/52818: The wm driver stops working after large traffic
> Date: Thu, 21 Dec 2017 01:22:38 +0900 (JST)
>
> This patch is a workaround of the 82583's errata.
>
> Index: if_wm.c
> ===================================================================
> RCS file: /export/cvsroot/netbsd/src/sys/dev/pci/if_wm.c,v
> retrieving revision 1.549
> diff -u -r1.549 if_wm.c
> --- if_wm.c 8 Dec 2017 05:22:23 -0000 1.549
> +++ if_wm.c 20 Dec 2017 16:07:06 -0000
> @@ -1851,6 +1851,43 @@
>
> wm_adjust_qnum(sc, pci_msix_count(pa->pa_pc, pa->pa_tag));
>
> + /*
> + * The 82573 disappears when PCIe ASPM L0s is enabled.
> + *
> + * The 82574 and 82583 does not support PCIe ASPM L0s with
> + * some chipset. The document of 82574 and 82583 says that
> + * disabling L0s with some specific chipset is sufficient,
> + * but we follow as of the Intel em driver does.
> + *
> + * References:
> + * Errata 8 of the Specification Update of i82573.
> + * Errata 20 of the Specification Update of i82574.
> + * Errata 9 of the Specification Update of i82583.
> + */
> + switch (sc->sc_type) {
> + int ok;
> + int capoff;
> +
> + case WM_T_82573:
> + case WM_T_82574:
> + case WM_T_82583:
> + ok = pci_get_capability(pc, pa->pa_tag,
> + PCI_CAP_PCIEXPRESS, &capoff, NULL);
> + if (!ok)
> + break;
> + reg = pci_conf_read(pc, pa->pa_tag, capoff + PCIE_LCAP);
> + if ((reg & PCIE_LCAP_ASPM) == 0)
> + break;
> + reg = pci_conf_read(pc, pa->pa_tag, capoff + PCIE_LCSR);
> + reg &= ~PCIE_LCSR_ASPM_L1;
> + reg &= ~PCIE_LCSR_ASPM_L0S;
> + pci_conf_write(pc, pa->pa_tag, capoff + PCIE_LCSR, reg);
> + aprint_verbose_dev(sc->sc_dev, "ASPM was disabled to workaround the errata.\n");
> + break;
> + default:
> + break;
> + }
> +
> /* Allocation settings */
> max_type = PCI_INTR_TYPE_MSIX;
> /*
>
>
Could you test the following patch?
---------
Add ASPM workaround for 8257[1234] and 82583.
Index: if_wm.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_wm.c,v
retrieving revision 1.550
diff -u -p -r1.550 if_wm.c
--- if_wm.c 28 Dec 2017 06:13:50 -0000 1.550
+++ if_wm.c 28 Dec 2017 12:03:45 -0000
@@ -921,6 +921,7 @@ static void wm_ulp_disable(struct wm_sof
static void wm_enable_phy_wakeup(struct wm_softc *);
static void wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
static void wm_enable_wakeup(struct wm_softc *);
+static void wm_disable_aspm(struct wm_softc *);
/* LPLU (Low Power Link Up) */
static void wm_lplu_d0_disable(struct wm_softc *);
/* EEE */
@@ -2048,6 +2049,9 @@ alloc_retry:
(sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI");
}
+ /* Disable ASPM L0s and/or L1 for workaround */
+ wm_disable_aspm(sc);
+
/* clear interesting stat counters */
CSR_READ(sc, WMREG_COLC);
CSR_READ(sc, WMREG_RXERRC);
@@ -2911,6 +2915,8 @@ wm_resume(device_t self, const pmf_qual_
{
struct wm_softc *sc = device_private(self);
+ /* Disable ASPM L0s and/or L1 for workaround */
+ wm_disable_aspm(sc);
wm_init_manageability(sc);
return true;
@@ -13806,6 +13812,66 @@ wm_enable_wakeup(struct wm_softc *sc)
pci_conf_write(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR, pmode);
}
+/* Disable ASPM L0s and/or L1 for workaround */
+static void
+wm_disable_aspm(struct wm_softc *sc)
+{
+ pcireg_t reg, mask = 0;
+ unsigned const char *str = "";
+
+ /*
+ * Only for PCIe device which has PCIe capability in the PCI config
+ * space.
+ */
+ if (((sc->sc_flags & WM_F_PCIE) == 0) || (sc->sc_pcixe_capoff == 0))
+ return;
+
+ switch (sc->sc_type) {
+ case WM_T_82571:
+ case WM_T_82572:
+ /*
+ * 8257[12] Errata 13: Device Does Not Support PCIe Active
+ * State Power management L1 State (ASPM L1).
+ */
+ mask = PCIE_LCSR_ASPM_L1;
+ str = "L1 is";
+ break;
+ case WM_T_82573:
+ case WM_T_82574:
+ case WM_T_82583:
+ /*
+ * The 82573 disappears when PCIe ASPM L0s is enabled.
+ *
+ * The 82574 and 82583 does not support PCIe ASPM L0s with
+ * some chipset. The document of 82574 and 82583 says that
+ * disabling L0s with some specific chipset is sufficient,
+ * but we follow as of the Intel em driver does.
+ *
+ * References:
+ * Errata 8 of the Specification Update of i82573.
+ * Errata 20 of the Specification Update of i82574.
+ * Errata 9 of the Specification Update of i82583.
+ */
+ mask = PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S;
+ str = "L0s and L1 are";
+ break;
+ default:
+ return;
+ }
+
+ reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
+ sc->sc_pcixe_capoff + PCIE_LCSR);
+ reg &= ~mask;
+ pci_conf_write(sc->sc_pc, sc->sc_pcitag,
+ sc->sc_pcixe_capoff + PCIE_LCSR, reg);
+
+ /* Print only in wm_attach() */
+ if ((sc->sc_flags & WM_F_ATTACHED) == 0)
+ aprint_verbose_dev(sc->sc_dev,
+ "ASPM %s disabled to workaround the errata.\n",
+ str);
+}
+
/* LPLU */
static void
---------
The same diff is at:
http://www.netbsd.org/~msaitoh/wm-aspm-20171228-0.dif
--
-----------------------------------------------
SAITOH Masanobu (msaitoh%execsw.org@localhost
msaitoh%netbsd.org@localhost)
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