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PR/42597 CVS commit: [netbsd-8] src
The following reply was made to PR port-amd64/42597; it has been noted by GNATS.
From: "Martin Husemann" <martin%netbsd.org@localhost>
Subject: PR/42597 CVS commit: [netbsd-8] src
Date: Tue, 21 Nov 2017 15:03:20 +0000
Module Name: src
Committed By: martin
Date: Tue Nov 21 15:03:20 UTC 2017
src/sys/arch/x86/include [netbsd-8]: specialreg.h
src/sys/arch/x86/x86 [netbsd-8]: cpu_topology.c identcpu.c
src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c
Pull up following revision(s) (requested by msaitoh in ticket #365):
sys/arch/x86/include/specialreg.h: revision 1.99
usr.sbin/cpuctl/arch/i386.c: revision 1.75
usr.sbin/cpuctl/arch/i386.c: revision 1.76
usr.sbin/cpuctl/arch/i386.c: revision 1.77
usr.sbin/cpuctl/arch/i386.c: revision 1.78
sys/arch/x86/x86/identcpu.c: revision 1.56
sys/arch/x86/x86/identcpu.c: revision 1.57
sys/arch/x86/x86/cpu_topology.c: revision 1.10
sys/arch/x86/include/specialreg.h: revision 1.100
sys/arch/x86/include/specialreg.h: revision 1.101
sys/arch/x86/include/specialreg.h: revision 1.102
sys/arch/x86/include/specialreg.h: revision 1.103
sys/arch/x86/include/specialreg.h: revision 1.104
sys/arch/x86/include/specialreg.h: revision 1.105
Add EFER_TCE. This would be an interesting feature to have, since it
reduces the indirect cost of invlpg; but I'm not convinced the way we
flush upper-levels is correct for this yet.
Fix typo in comment
Add a comment about APICBASE_PHYSADDR. Has to do with PR/42597.
Define CPUID Fn00000001 %ebx bits and use them. No functional change.
Set ci->ci_cflush_lsize correctly. This bug was added in the last commit(1.56).
Add the following instruction bits in Structured Extended Flags Enumeration
Leaf from "Intel Architecture Instruction Set Extensions and Future Features
Programming Reference" (319433-030):
- Print ci_feat_val (Structured Extended Feature leaf Fn0000_0007 %ebx) on
- Print ci_feat_val (Fn0000_0007 %ecx) on Intel.
Update from the latest Intel SDM:
0x5c: Atom (Goldmont)
0x5f: Atom (Goldmont, Denverton)
0x7a: Atom (Goldmont Plus)
Add Turbo Boost Max Technology 3.0 bit.
Update from Intel SDM:
0x55: Xeon Scalable (Skylake)
0x57: Xeon Phi 200 (Knights Landing)
0x66: Future Core (Cannon Lake)
0x85: Future Xeon Phi (Knights Mill)
Add the following bits in AMD Fn8000000a %edx features (SVM features):
PFThreshold (PAUSE filter threshold)
AVIC (AMD virtual interrupt controller)
V_VMSAVE_VMLOAD (virtualized VMSAVE and VMLOAD)
vGIF (virtualized GIF)
To generate a diff of this commit:
cvs rdiff -u -r1.98 -r184.108.40.206 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.9 -r220.127.116.11 src/sys/arch/x86/x86/cpu_topology.c
cvs rdiff -u -r1.55 -r18.104.22.168 src/sys/arch/x86/x86/identcpu.c
cvs rdiff -u -r1.74 -r22.214.171.124 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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