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Re: port-arm/52163: support for gpio for Xscale
The following reply was made to PR port-arm/52163; it has been noted by GNATS.
From: smesgr <smesgr%gmail.com@localhost>
To: gnats-bugs%NetBSD.org@localhost, port-arm-maintainer%netbsd.org@localhost,
gnats-admin%netbsd.org@localhost, netbsd-bugs%netbsd.org@localhost
Cc:
Subject: Re: port-arm/52163: support for gpio for Xscale
Date: Wed, 7 Jun 2017 19:28:59 +0200
Patch changed according Matts suggestion. Tested with an Gumstix with
(Intel build) PXA250 and (Marvell build) PX270:
Index: distrib/sets/lists/man/mi
===================================================================
RCS file: /cvsroot/src/distrib/sets/lists/man/mi,v
retrieving revision 1.1557
diff -u -r1.1557 mi
--- distrib/sets/lists/man/mi 27 May 2017 21:02:55 -0000 1.1557
+++ distrib/sets/lists/man/mi 7 Jun 2017 16:56:37 -0000
@@ -1579,6 +1579,7 @@
./usr/share/man/cat4/puffs.0 man-puffs-catman .cat
./usr/share/man/cat4/pwdog.0 man-sys-catman .cat
./usr/share/man/cat4/px.0 man-sys-catman .cat
+./usr/share/man/cat4/pxagpio.0 man-sys-catman .cat
./usr/share/man/cat4/pxaip.0 man-sys-catman .cat
./usr/share/man/cat4/pxg.0 man-sys-catman .cat
./usr/share/man/cat4/qe.0 man-sys-catman .cat
@@ -4629,6 +4630,7 @@
./usr/share/man/html4/puffs.html man-sys-htmlman html
./usr/share/man/html4/pwdog.html man-sys-htmlman html
./usr/share/man/html4/px.html man-sys-htmlman html
+./usr/share/man/html4/pxagpio.html man-sys-htmlman html
./usr/share/man/html4/pxaip.html man-sys-htmlman html
./usr/share/man/html4/pxg.html man-sys-htmlman html
./usr/share/man/html4/qe.html man-sys-htmlman html
@@ -7581,6 +7583,7 @@
./usr/share/man/man4/puffs.4 man-sys-man .man
./usr/share/man/man4/pwdog.4 man-sys-man .man
./usr/share/man/man4/px.4 man-sys-man .man
+./usr/share/man/man4/pxagpio.4 man-sys-man .man
./usr/share/man/man4/pxaip.4 man-sys-man .man
./usr/share/man/man4/pxg.4 man-sys-man .man
./usr/share/man/man4/qe.4 man-sys-man .man
Index: share/man/man4/Makefile
===================================================================
RCS file: /cvsroot/src/share/man/man4/Makefile,v
retrieving revision 1.637
diff -u -r1.637 Makefile
--- share/man/man4/Makefile 27 May 2017 21:02:55 -0000 1.637
+++ share/man/man4/Makefile 7 Jun 2017 16:56:37 -0000
@@ -50,8 +50,8 @@
pad.4 pas.4 pcdisplay.4 pcf8563rtc.4 pciide.4 pckbc.4 pckbd.4 pcn.4 \
pcppi.4 pcscp.4 pcweasel.4 pdcide.4 pdcsata.4 piixide.4 piixpcib.4 \
piixpm.4 pim.4 plip.4 pm3fb.4 pms.4 pmu.4 pnaphy.4 ppbus.4 ppp.4
pppoe.4 \
- pseye.4 ptcd.4 ptm.4 pty.4 puc.4 pud.4 puffs.4 pwdog.4 px.4 pxaip.4 \
- pxg.4 qe.4 qec.4 qsphy.4 \
+ pseye.4 ptcd.4 ptm.4 pty.4 puc.4 pud.4 puffs.4 pwdog.4 px.4 pxagpio.4 \
+ pxaip.4 pxg.4 qe.4 qec.4 qsphy.4 \
raid.4 ral.4 ray.4 rcons.4 rdcphy.4 re.4 rgephy.4 rlphy.4 \
rnd.4 route.4 rs5c372rtc.4 rtk.4 rtsx.4 rtw.4 rtwn.4 rum.4 run.4 \
s390rtc.4 satalink.4 sbus.4 scc.4 schide.4 \
Index: share/man/man4/pxagpio.4
===================================================================
RCS file: share/man/man4/pxagpio.4
diff -N share/man/man4/pxagpio.4
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ share/man/man4/pxagpio.4 7 Jun 2017 17:21:50 -0000
@@ -0,0 +1,65 @@
+.\"
+.\" Copyright (c) 2017 The NetBSD Foundation, Inc.
+.\" All rights reserved.
+.\"
+.\" This code is derived from software contributed to The NetBSD Foundation
+.\" by Steve Woodford.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND
CONTRIBUTORS
+.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED
+.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR
+.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR
CONTRIBUTORS
+.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
BUSINESS
+.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
OF THE
+.\" POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd April 15, 2017
+.Dt PXAGPIO 4
+.Os
+.Sh NAME
+.Nm pxaip
+.Nd Intel Xscale PXA250/PXA270 GPIO Controller
+.Sh SYNOPSIS
+.Cd "pxagpio* at pxaip?"
+.Cd "gpio* at gpiobus?"
+.Sh DESCRIPTION
+.Nm
+is an on-board GPIO controller found in XScale PXA250, PXA255, PXA270,
+PXA271, PXA272 and PXA273 processors manufactured by Intel and Marvell
Technology.
+The driver does support either 86 pins for PXA250 and 121 pins for
PXA270 processor family.
+Access to the pins is provided by the
+.Xr gpio 4
+interface. The driver does support GPIO_PIN_INPUT and GPIO_PIN_OUTPUT.
+GPIO pins being used in alternate configurations are not available
+for GPIO operations.
+.Sh SEE ALSO
+.Xr gpio 4 ,
+.Xr pxagpio 4
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Nx 2.0 . GPIO attachment appeared in
+.Nx 8.0 .
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+driver was written by
+.An Steve Woodford
+.Aq Mt scw%NetBSD.org@localhost .
+This manual page was contributed by
+.An Stephan Meisinger .
Index: sys/arch/arm/xscale/files.pxa2x0
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/files.pxa2x0,v
retrieving revision 1.18
diff -u -r1.18 files.pxa2x0
--- sys/arch/arm/xscale/files.pxa2x0 6 Jun 2012 20:21:45 -0000 1.18
+++ sys/arch/arm/xscale/files.pxa2x0 7 Jun 2017 16:56:37 -0000
@@ -21,7 +21,7 @@
defflag opt_pxa2x0_gpio.h PXAGPIO_HAS_GPION_INTRS
# GPIO controller
-device pxagpio
+device pxagpio: gpiobus
attach pxagpio at pxaip
file arch/arm/xscale/pxa2x0_gpio.c pxagpio needs-flag
Index: sys/arch/arm/xscale/pxa2x0_gpio.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/pxa2x0_gpio.c,v
retrieving revision 1.16
diff -u -r1.16 pxa2x0_gpio.c
--- sys/arch/arm/xscale/pxa2x0_gpio.c 12 Nov 2012 18:00:38 -0000 1.16
+++ sys/arch/arm/xscale/pxa2x0_gpio.c 7 Jun 2017 16:56:37 -0000
@@ -38,6 +38,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pxa2x0_gpio.c,v 1.16 2012/11/12 18:00:38
skrll Exp $");
+#include "gpio.h"
#include "opt_pxa2x0_gpio.h"
#include <sys/param.h>
@@ -55,6 +56,9 @@
#include "locators.h"
+#include <sys/gpio.h>
+#include <dev/gpio/gpiovar.h>
+
struct gpio_irq_handler {
struct gpio_irq_handler *gh_next;
int (*gh_func)(void *);
@@ -75,11 +79,19 @@
#else
struct gpio_irq_handler *sc_handlers[2];
#endif
+ struct gpio_chipset_tag sc_gpio_gc;
+ gpio_pin_t sc_gpio_pins[GPIO_NPINS];
};
static int pxagpio_match(device_t, cfdata_t, void *);
static void pxagpio_attach(device_t, device_t, void *);
+#if NGPIO > 0
+static int pxa2x0_gpio_pin_read(void *, int);
+static void pxa2x0_gpio_pin_write(void *, int, int);
+static void pxa2x0_gpio_pin_ctl(void *, int, int);
+#endif
+
CFATTACH_DECL_NEW(pxagpio, sizeof(struct pxagpio_softc),
pxagpio_match, pxagpio_attach, NULL, NULL);
@@ -137,6 +149,11 @@
{
struct pxagpio_softc *sc = device_private(self);
struct pxaip_attach_args *pxa = aux;
+#if NGPIO > 0
+ struct gpiobus_attach_args gba;
+ int pin, maxpin;
+ u_int func;
+#endif
sc->sc_dev = self;
sc->sc_bust = pxa->pxa_iot;
@@ -185,6 +202,42 @@
sc->sc_irqcookie[0] = sc->sc_irqcookie[1] = NULL;
pxagpio_softc = sc;
+#if NGPIO > 0
+#if defined(CPU_XSCALE_PXA250) && defined(CPU_XSCALE_PXA270)
+ maxpin = CPU_IS_PXA270 ? PXA270_GPIO_NPINS : PXA250_GPIO_NPINS;
+#else
+ maxpin = GPIO_NPINS;
+#endif
+ for (pin = 0; pin < maxpin; ++pin) {
+
+ sc->sc_gpio_pins[pin].pin_num = pin;
+ func = pxa2x0_gpio_get_function(pin);
+
+ if (GPIO_IS_GPIO(func)) {
+ sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT |
+ GPIO_PIN_OUTPUT;
+ sc->sc_gpio_pins[pin].pin_state =
+ pxa2x0_gpio_pin_read(sc, pin);
+ } else {
+ sc->sc_gpio_pins[pin].pin_caps = 0;
+ sc->sc_gpio_pins[pin].pin_state = 0;
+ }
+ }
+
+ /* create controller tag */
+ sc->sc_gpio_gc.gp_cookie = sc;
+ sc->sc_gpio_gc.gp_pin_read = pxa2x0_gpio_pin_read;
+ sc->sc_gpio_gc.gp_pin_write = pxa2x0_gpio_pin_write;
+ sc->sc_gpio_gc.gp_pin_ctl = pxa2x0_gpio_pin_ctl;
+
+ gba.gba_gc = &sc->sc_gpio_gc;
+ gba.gba_pins = sc->sc_gpio_pins;
+ gba.gba_npins = maxpin;
+
+ config_found_ia(self, "gpiobus", &gba, gpiobus_print);
+#else
+ aprint_normal_dev(sc->sc_dev, "no GPIO configured in kernel\n");
+#endif
}
void
@@ -668,6 +721,35 @@
splx(s);
}
+#if NGPIO > 0
+/* GPIO support functions */
+static int
+pxa2x0_gpio_pin_read(void *arg, int pin)
+{
+ return pxa2x0_gpio_get_bit(pin);
+}
+
+static void
+pxa2x0_gpio_pin_write(void *arg, int pin, int value)
+{
+ if (value == GPIO_PIN_HIGH) {
+ pxa2x0_gpio_set_bit(pin);
+ } else {
+ pxa2x0_gpio_clear_bit(pin);
+ }
+}
+
+static void
+pxa2x0_gpio_pin_ctl(void *arg, int pin, int flags)
+{
+ if (flags & GPIO_PIN_OUTPUT) {
+ pxa2x0_gpio_set_function(pin, GPIO_OUT);
+ } else if (flags & GPIO_PIN_INPUT) {
+ pxa2x0_gpio_set_function(pin, GPIO_IN);
+ }
+}
+#endif
+
#if defined(CPU_XSCALE_PXA250)
/*
Index: sys/arch/evbarm/conf/GUMSTIX
Index: sys/arch/evbarm/conf/GUMSTIX
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/conf/GUMSTIX,v
retrieving revision 1.90
diff -u -r1.90 GUMSTIX
--- sys/arch/evbarm/conf/GUMSTIX 19 Feb 2017 07:47:00 -0000 1.90
+++ sys/arch/evbarm/conf/GUMSTIX 7 Jun 2017 16:56:37 -0000
@@ -179,6 +181,7 @@
options PXAGPIO_HAS_GPION_INTRS
pxagpio0 at pxaip? # GPIO
+gpio* at gpiobus?
pxartc0 at pxaip? addr 0x40900000 # RTC
# cotulla integrated 16550 UARTs
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