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kern/49229: pm2fb are not attached on Sparc64 and Alpha.



>Number:         49229
>Category:       kern
>Synopsis:       pm2fb are not attached on Sparc64 and Alpha.
>Confidential:   no
>Severity:       non-critical
>Priority:       high
>Responsible:    kern-bug-people
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Sat Sep 20 17:50:00 +0000 2014
>Originator:     nullnilaki
>Release:        NetBSD 7.99.1
>Organization:
Japan
>Environment:
NetBSD 7.99.1 (GENERIC) #42: Sat Sep 20 06:03:16 UTC 2014
        naruaki@:/usr/obj.sparc64/sys/arch/sparc64/compile/GENERIC
NetBSD 7.99.1 (GENERIC-$Revision: 1.360 $) #82: Sat Sep 20 04:23:43 UTC 2014
        naruaki@:/usr/obj.alpha/sys/arch/alpha/compile/GENERIC

>Description:
I have Raptor GFX(rev -06 REV.50) and  ELSA Gloria Synergy.
See:
https://twitter.com/nullnilaki/status/507165743436136448/photo/1(Raptor GFX)
https://twitter.com/nullnilaki/status/513144784530071552/photo/1(Raptor GFX)
https://twitter.com/nullnilaki/status/498520770247532544/photo/1(Gloria Synergy)
https://twitter.com/nullnilaki/status/498521241616007168/photo/1(Gloria Synergy)

This card has Permedia2 ("TVP4020") chip.

pm2fb is not supported on Alpha.
==========================================================================
pci2: i/o space, memory space enabled, rd/line, wr/inv ok
vga0 at pci2 dev 9 function 0: vendor 0x104c product 0x3d07 (rev. 0x01)
wsdisplay0 at vga0 kbdmux 1: console (80x25, vt100 emulation), using wskbd0
wsmux1: connecting to wsdisplay0
drm at vga0 not configured
==========================================================================

pm2fb is supported, but Permedia2("TVP4020") chip is not supported on Sparc64.
==========================================================================
pci10 at ppb9 bus 12
pci10: i/o space, memory space enabled
genfb0 at pci10 dev 1 function 0: Texas Instruments TVP4020 Permedia 2 (rev. 
0x11)
genfb0: framebuffer at 0x1000000, size 1280x1024, depth 32, stride 5120
wsdisplay0 at genfb0 kbdmux 1: console (default, vt100 emulation)
wsmux1: connecting to wsdisplay0
wsdisplay0: screen 1-3 added (default, vt100 emulation)
drm at genfb0 not configured
==========================================================================

>How-To-Repeat:

>Fix:
==========================================================================
diff -Naru pci.orig/pm2fb.c pci/pm2fb.c
--- pci.orig/pm2fb.c    2014-09-19 23:39:30.000000000 +0000
+++ pci/pm2fb.c 2014-09-19 23:53:38.000000000 +0000
@@ -184,6 +184,9 @@
 
 /* mode setting stuff */
 static int pm2fb_set_pll(struct pm2fb_softc *, int);
+static void pm2fb_set_dac(struct pm2fb_softc *, const struct videomode *);
+static int pm2vfb_set_pll(struct pm2fb_softc *, int);
+static void pm2vfb_set_dac(struct pm2fb_softc *, const struct videomode *);
 static uint8_t pm2fb_read_dac(struct pm2fb_softc *, int);
 static void pm2fb_write_dac(struct pm2fb_softc *, int, uint8_t);
 static void pm2fb_set_mode(struct pm2fb_softc *, const struct videomode *);
@@ -226,6 +229,28 @@
                     -1,              -1,              -1,              -1,
                     0};
 
+const struct {
+        int vendor;
+        int product;
+        int flags;
+} pm2fb_pci_devices[] = {
+        {
+                PCI_VENDOR_3DLABS,
+                PCI_PRODUCT_3DLABS_PERMEDIA2V,
+                0
+        },
+        {
+                PCI_VENDOR_TI,
+                PCI_PRODUCT_TI_TVP4020,
+                1      
+        },
+        {
+                0,
+                0,
+                0
+        }
+};
+
 static inline void
 pm2fb_wait(struct pm2fb_softc *sc, int slots)
 {
@@ -250,26 +275,24 @@
                while (bus_space_read_4(sc->sc_memt, sc->sc_regh, 
                        PM2_OUTPUT_FIFO_WORDS) == 0);
        } while (bus_space_read_4(sc->sc_memt, sc->sc_regh, PM2_OUTPUT_FIFO) != 
-           0x188);
+           PM2_SYNC_TAG);
 }
 
 static int
 pm2fb_match(device_t parent, cfdata_t match, void *aux)
 {
+       int i;
        struct pci_attach_args *pa = (struct pci_attach_args *)aux;
 
        if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY)
                return 0;
-       if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_3DLABS)
-               return 0;
 
-       /*
-        * only card tested on so far is a TechSource Raptor GFX 8P /
-        * Sun PGX32, which happens to be a Permedia 2v
-        */
-       if (/*(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DLABS_PERMEDIA2) ||*/
-           (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DLABS_PERMEDIA2V))
-               return 100;
+       for (i = 0; pm2fb_pci_devices[i].vendor; i++) {
+               if ((PCI_VENDOR(pa->pa_id) == pm2fb_pci_devices[i].vendor &&
+                    PCI_PRODUCT(pa->pa_id) == pm2fb_pci_devices[i].product)) 
+                       return 100;
+       }
+
        return (0);
 }
 
@@ -292,8 +315,14 @@
        sc->sc_memt = pa->pa_memt;
        sc->sc_iot = pa->pa_iot;
        sc->sc_dev = self;
-       sc->sc_is_pm2 = (PCI_PRODUCT(pa->pa_id) == 
-           PCI_PRODUCT_3DLABS_PERMEDIA2);
+
+       for (i = 0; pm2fb_pci_devices[i].vendor; i++) {
+               if (PCI_PRODUCT(pa->pa_id) == pm2fb_pci_devices[i].product) {
+                       sc->sc_is_pm2 = pm2fb_pci_devices[i].flags ;
+                       break;
+               }
+       }
+
        pci_aprint_devinfo(pa, NULL);
 
        /*
@@ -325,8 +354,13 @@
 
        prop_dictionary_get_bool(dict, "is_console", &is_console);
 
-       pci_mapreg_info(pa->pa_pc, pa->pa_tag, 0x14, PCI_MAPREG_TYPE_MEM,
+#if BYTE_ORDER == LITTLE_ENDIAN
+       pci_mapreg_info(pa->pa_pc, pa->pa_tag, PM2_PCI_MEM_LE, 
PCI_MAPREG_TYPE_MEM,
            &sc->sc_fb, &sc->sc_fbsize, &flags);
+#else
+        pci_mapreg_info(pa->pa_pc, pa->pa_tag, PM2_PCI_MEM_BE, 
PCI_MAPREG_TYPE_MEM,
+            &sc->sc_fb, &sc->sc_fbsize, &flags);
+#endif
 
        if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_MEM, 0,
            &sc->sc_memt, &sc->sc_regh, &sc->sc_reg, &sc->sc_regsize)) {
@@ -727,13 +761,14 @@
 static void
 pm2fb_write_dac(struct pm2fb_softc *sc, int reg, uint8_t data)
 {
-       pm2fb_wait(sc, 3);
        if (sc->sc_is_pm2) {
+               pm2fb_wait(sc, 2);
                bus_space_write_1(sc->sc_memt, sc->sc_regh,
                    PM2_DAC_PAL_WRITE_IDX, reg);
                bus_space_write_1(sc->sc_memt, sc->sc_regh,
                    PM2_DAC_INDEX_DATA, data);
        } else {
+               pm2fb_wait(sc, 3);
                bus_space_write_1(sc->sc_memt, sc->sc_regh,
                    PM2V_DAC_INDEX_LOW, reg & 0xff);
                bus_space_write_1(sc->sc_memt, sc->sc_regh,
@@ -998,6 +1033,16 @@
                        data = (uint8_t *)font->data + uc * ri->ri_fontscale;
 
                        mode = PM2RM_MASK_MIRROR;
+#if BYTE_ORDER == LITTLE_ENDIAN
+                       switch (ri->ri_font->stride) {
+                               case 1:
+                                       mode |= 4 << 7;
+                                       break;
+                               case 2:
+                                       mode |= 3 << 7;
+                                       break;
+                       }
+#else
                        switch (ri->ri_font->stride) {
                                case 1:
                                        mode |= 3 << 7;
@@ -1006,7 +1051,7 @@
                                        mode |= 2 << 7;
                                        break;
                        }
-
+#endif
                        pm2fb_wait(sc, 8);
 
                        bus_space_write_4(sc->sc_memt, sc->sc_regh,
@@ -1449,21 +1494,17 @@
        return (i2c_bitbang_write_byte(cookie, val, flags, &pm2fb_i2cbb_ops));
 }
 
-#define RefClk 14318   /* all frequencies are in kHz */
 static int
-pm2fb_set_pll(struct pm2fb_softc *sc, int freq)
+pm2vfb_set_pll(struct pm2fb_softc *sc, int freq)
 {
        int m, n, p, diff, out_freq, bm = 1, bn = 3, bp = 0,
            bdiff = 1000000 /* , bfreq */;
        int fi;
        uint8_t temp;
 
-       /*
-        * this should work on PM2V, PM2 needs something slightly different
-        */
        for (m = 1; m < 128; m++) {
                for (n = 2 * m + 1; n < 256; n++) {
-                       fi = RefClk * n / m;
+                       fi = PM2_EXT_CLOCK_FREQ * n / m;
                        for (p = 0; p < 2; p++) {
                                out_freq = fi >> (p + 1);
                                diff = abs(out_freq - freq);
@@ -1495,12 +1536,124 @@
        return 0;
 }
 
+static int
+pm2fb_set_pll(struct pm2fb_softc *sc, int freq)
+{
+        uint8_t  reg, bm = 0, bn = 0, bp = 0;
+        unsigned int  m, n, p, fi, diff, out_freq, bdiff = 1000000;
+
+        for (n = 2; n < 15; n++) {
+                for (m = 2 ; m < 256; m++) {
+                        fi = PM2_EXT_CLOCK_FREQ * m / n;
+                        if (fi >= PM2_PLL_FREQ_MIN && fi <= PM2_PLL_FREQ_MAX) {
+                                for (p = 0; p < 5; p++) {
+                                        out_freq = fi >> p;
+                                        diff = abs(out_freq - freq);
+                                        if (diff < bdiff) {
+                                                bm = m;
+                                                bn = n;
+                                                bp = p;
+                                                bdiff = diff;
+                                       }
+                               }
+                        }
+                }
+        }
+
+       pm2fb_write_dac(sc, PM2_DAC_PIXELCLKA_M, bm);
+       pm2fb_write_dac(sc, PM2_DAC_PIXELCLKA_N, bn);
+       pm2fb_write_dac(sc, PM2_DAC_PIXELCLKA_P, (bp | 0x08));
+
+       do {
+               reg = bus_space_read_1(sc->sc_memt, sc->sc_regh,
+                       PM2_DAC_INDEX_DATA);
+       } while (reg == PCLK_LOCKED);
+
+       return 0;
+}
+
+/*
+ * most of the following was adapted from the xf86-video-glint driver's
+ * pm2_dac.c (8bpp only)
+ */
+static void 
+pm2fb_set_dac(struct pm2fb_softc *sc, const struct videomode *mode)
+{
+       int t1, t2, t3, t4, stride;
+       uint32_t vclk, tmp;
+       uint8_t sync = 0;
+       
+       t1 = mode->hsync_start - mode->hdisplay;
+       t2 = mode->vsync_start - mode->vdisplay;
+       t3 = mode->hsync_end - mode->hsync_start;
+       t4 = mode->vsync_end - mode->vsync_start;
+
+       /* first round up to the next multiple of 32 */
+       stride = (mode->hdisplay + 31) & ~31;
+       /* then find the next bigger one that we have partial products for */
+       while ((partprodPermedia[stride >> 5] == -1) && (stride < 2048)) {
+               stride += 32;
+       }
+
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_HTOTAL, 
+           ((mode->htotal) >> 2) - 1);
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_HSYNC_END,
+           (t1 + t3) >> 2);
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_HSYNC_START,
+           (t1 >> 2));
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_HBLANK_END,
+           (mode->htotal - mode->hdisplay) >> 2);
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_HGATE_END,
+           (mode->htotal - mode->hdisplay) >> 2);
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_SCREEN_STRIDE,  
+           stride >> 3);
+
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_VTOTAL, 
+           mode->vtotal - 2);
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_VSYNC_END,
+           t2 + t4 - 1);
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_VSYNC_START,
+           t2 - 1);
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_VBLANK_END,
+           mode->vtotal - mode->vdisplay);
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_VIDEO_CONTROL,
+           PM2_VC_VIDEO_ENABLE | 
+           PM2_VC_HSYNC_ACT_HIGH | PM2_VC_VSYNC_ACT_HIGH);
+
+       vclk = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM2_VCLKCTL);
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_VCLKCTL,
+           vclk & 0xfffffffc);
+
+       tmp = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM2_CHIP_CONFIG);
+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_CHIP_CONFIG, tmp & 
0xffffffdd);
+
+       pm2fb_write_dac(sc, PM2_DAC_MODE_CONTROL, MOC_BUFFERFRONT);
+       pm2fb_set_pll(sc, mode->dot_clock);     
+
+       sync = MC_PALETTE_8BIT;
+
+       if (!(mode->flags & VID_PHSYNC))
+           sync |= MC_HSYNC_INV;
+       if (!(mode->flags & VID_PVSYNC))
+           sync |= MC_VSYNC_INV;
+
+       pm2fb_write_dac(sc, PM2_DAC_MISC_CONTROL, sync);
+       pm2fb_write_dac(sc, PM2_DAC_COLOR_MODE, CM_PALETTE | CM_GUI_ACTIVE | 
CM_RGB);
+
+       sc->sc_width = mode->hdisplay;
+       sc->sc_height = mode->vdisplay;
+       sc->sc_depth = 8;
+       sc->sc_stride = stride;
+       aprint_normal_dev(sc->sc_dev, "pm2fb using %d x %d in 8 bit, stride 
%d\n",
+           sc->sc_width, sc->sc_height, stride);
+}
+
 /*
  * most of the following was adapted from the xf86-video-glint driver's
  * pm2v_dac.c
  */                            
 static void
-pm2fb_set_mode(struct pm2fb_softc *sc, const struct videomode *mode)
+pm2vfb_set_dac(struct pm2fb_softc *sc, const struct videomode *mode)
 {
        int t1, t2, t3, t4, stride;
        uint32_t vclk;
@@ -1548,7 +1701,7 @@
        bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_VCLKCTL,
            vclk & 0xfffffffc);
 
-       pm2fb_set_pll(sc, mode->dot_clock / 2);
+       pm2vfb_set_pll(sc, mode->dot_clock / 2);
        pm2fb_write_dac(sc, PM2V_DAC_MISC_CONTROL, PM2V_DAC_8BIT);
 
        if (mode->flags & VID_PHSYNC)
@@ -1563,6 +1716,16 @@
        sc->sc_height = mode->vdisplay;
        sc->sc_depth = 8;
        sc->sc_stride = stride;
-       aprint_normal_dev(sc->sc_dev, "using %d x %d in 8 bit, stride %d\n",
+       aprint_normal_dev(sc->sc_dev, "pm2vfb using %d x %d in 8 bit, stride 
%d\n",
            sc->sc_width, sc->sc_height, stride);
 }
+
+static void
+pm2fb_set_mode(struct pm2fb_softc *sc, const struct videomode *mode)
+{
+        if (sc->sc_is_pm2) {
+                pm2fb_set_dac(sc, mode);
+        } else {
+                pm2vfb_set_dac(sc, mode);
+        }      
+}
diff -Naru pci.orig/pm2reg.h pci/pm2reg.h
--- pci.orig/pm2reg.h   2014-09-19 23:26:35.000000000 +0000
+++ pci/pm2reg.h        2014-09-16 16:07:02.000000000 +0000
@@ -33,6 +33,14 @@
 #ifndef PM2_REG_H
 #define PM2_REG_H
 
+/* all frequencies are in kHz */
+#define        PM2_EXT_CLOCK_FREQ              14318
+#define        PM2_PLL_FREQ_MIN                150000
+#define        PM2_PLL_FREQ_MAX                300000
+
+#define PM2_PCI_MEM_LE         0x14    /* Framebuffer (little-endian) */
+#define PM2_PCI_MEM_BE         0x18    /* Framebuffer (big-endian) */
+
 #define PM2_RESET      0x00000000      /* any write initiates a chip reset */
 #define                PM2_RESET_BUSY  0x80000000      /* reset in progress */
 
@@ -54,6 +62,7 @@
 #define                PM2_AP_PACKED16_READ_B  0x00000010 /* Buffer A 
otherwise */
 #define                PM2_AP_PACKED16_WRITE_B 0x00000020 /* A otherwise */
 #define                PM2_AP_PACKED16_WRT_DBL 0x00000040
+#define        PM2_CHIP_CONFIG         0x00000070
 #define                PM2_AP_PACKED16_R31     0x00000080 /* read buffer 
selected by
                                                    * visibility bit in memory 
                                                    */
@@ -64,6 +73,8 @@
 #define PM2_FB_WRITE_MASK      0x00001140
 
 #define PM2_OUTPUT_FIFO                0x00002000
+#define         PM2_SYNC_TAG           0x00000188
+
 
 #define PM2_SCREEN_BASE                0x00003000 /* in 64bit units */
 #define PM2_SCREEN_STRIDE      0x00003008 /* in 64bit units */
@@ -146,10 +157,13 @@
 #define                CM_RGB565       0x06
 #define                CM_RGBA8888     0x08
 #define                CM_RGB888       0x09
-#define                CM_GUI_DISABLE  0x10
+#define                CM_GUI_ACTIVE   0x10
 #define                CM_RGB          0x20    /* BGR otherwise */
 #define                CM_TRUECOLOR    0x80    /* use palette for gamma 
correction */
 
+#define PM2_DAC_MODE_CONTROL   0x19
+#define                MOC_BUFFERFRONT 0x00
+
 #define PM2_DAC_MISC_CONTROL   0x1e
 #define                MC_POWERDOWN    0x01
 #define                MC_PALETTE_8BIT 0x02    /* 6bit otherwise */

--------------------------------------------------------------------------

diff -Naru conf.orig/GENERIC conf/GENERIC
--- conf.orig/GENERIC   2014-09-20 00:06:45.000000000 +0000
+++ conf/GENERIC        2014-09-20 00:03:49.000000000 +0000
@@ -360,6 +360,7 @@
 viaide* at     pci? dev ? function ?           # VIA/AMD/Nvidia IDE controllers
 pcn*   at      pci? dev ? function ?           # AMD PCnet-PCI Ethernet
 pcscp* at      pci? dev ? function ?           # AMD Am53c974 PCscsi-PCI
+pm2fb*  at      pci? dev ? function ?           # 3Dlabs Permedia 2 Graphics
 ppb*   at      pci? dev ? function ?           # PCI-PCI Bridges
 puc*   at      pci? dev ? function ?           # PCI "universal" comm. cards
 radeonfb* at   pci? dev ? function ?           # ATI/AMD Radeon Graphics
@@ -707,6 +708,7 @@
 wsdisplay*     at      tfb?
 wsdisplay*     at      sfb?
 #wsdisplay*    at      sfbp?
+wsdisplay*     at      pm2fb?
 wsdisplay*     at      px?
 wsdisplay*     at      pxg?
 wsdisplay*     at      radeonfb?
==========================================================================

Commentary1:
==========================================================================
>+#if BYTE_ORDER == LITTLE_ENDIAN
>+      pci_mapreg_info(pa->pa_pc, pa->pa_tag, PM2_PCI_MEM_LE, 
>PCI_MAPREG_TYPE_MEM,
>           &sc->sc_fb, &sc->sc_fbsize, &flags);
>+#else
>+        pci_mapreg_info(pa->pa_pc, pa->pa_tag, PM2_PCI_MEM_BE, 
>PCI_MAPREG_TYPE_MEM,
>+            &sc->sc_fb, &sc->sc_fbsize, &flags);
>+#endif

IF Byte order of Host processors and framebuffer were swapped, X gets corrupted 
with wsfb driver. 
(For example, Sparc64 system and framebuffer was mapped of little-endian mode.)
See:
https://twitter.com/nullnilaki/status/511297979018248192/photo/1
But,that hasn't been implemented yet.
I wonder why this problem is not happen so far.
Permedia2v is special?
==========================================================================

Commentary2:
==========================================================================
+#if BYTE_ORDER == LITTLE_ENDIAN
+                       switch (ri->ri_font->stride) {
+                               case 1:
+                                       mode |= 4 << 7;
+                                       break;
+                               case 2:
+                                       mode |= 3 << 7;
+                                       break;
+                       }
+#else
                        switch (ri->ri_font->stride) {
                                case 1:
                                        mode |= 3 << 7;
@@ -1006,7 +1051,7 @@
                                        mode |= 2 << 7;
                                        break;
                        }
-
+#endif

Sparc64:
I'm sorry that I only tested ri_font->stride is "2" in pm2fb_putchar.
I don't know how to use(display) ri_font->stride is "1" mode.
Please teach me how to use ri_font->stride is "1".

Alpha:
I'm sorry that I only tested ri_font->stride is "2" in pm2fb_putchar.
I don't know how to use(display) ri_font->stride is "1" mode and
pm2fb_putchar_aa.
Please teach me how to use pm2fb_putchar_aa.
==========================================================================

commentary3:
==========================================================================
>+       tmp = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM2_CHIP_CONFIG);
>+       bus_space_write_4(sc->sc_memt, sc->sc_regh, PM2_CHIP_CONFIG, tmp & 
>0xffffffdd);

This code is need.
Otherwise, ELSA Gloria Synergy is Black out.
==========================================================================

commentary4:
==========================================================================
>-#define               CM_GUI_DISABLE  0x10
>+#define               CM_GUI_ACTIVE   0x10

This means CM_GUI_ACTIVE.
==========================================================================

pm2fb framebuffer console and X11 with wsfb driver work fine on Sparc64.
==========================================================================
https://twitter.com/nullnilaki/status/511293966407323648/photo/1
https://twitter.com/nullnilaki/status/511558388463833088/photo/1
pm2fb0 at pci10 dev 1 function 0: Texas Instruments TVP4020 Permedia 2 (rev. 
0x11)
pm2fb0: 8 MB aperture at 0x01800000
no data for est. mode 640x480x67
pm2fb0: pm2fb using 1280 x 1024 in 8 bit, stride 1280
wsdisplay0 at pm2fb0 kbdmux 1: console (default, vt100 emulation)
==========================================================================

X11 with wsfb driver work fine on Alpha.
==========================================================================
https://twitter.com/nullnilaki/status/511363128567660544/photo/1
https://twitter.com/nullnilaki/status/511315633493929985/photo/1
pm2fb0 at pci2 dev 9 function 0: vendor 0x104c product 0x3d07 (rev. 0x01)
pm2fb0: no width property
pm2fb0: no height property
pm2fb0: no depth property
pm2fb0: 8 MB aperture at 0x01000000
pm2fb0: pm2fb using 1280 x 1024 in 8 bit, stride 1280
==========================================================================

But pm2fb framebuffer console has some problem.
Current status and issues of the Alpha(little-endian system?).

1.Slanted at an angle of 2 degrees to the perpendicular.
See:
https://twitter.com/nullnilaki/status/513148572682813440/photo/1
https://twitter.com/nullnilaki/status/513149617920163840/photo/1
I think that this is pm2fb_bitblt's problem.
(I apologize if I've interpreted that incorrectly.)
Please fix this problem.
Gloria Synergy is very precious card on Alpha,
Because it is implemented framebuffer console!
See:
Graphic Card Compatibility List
http://moon.hanya-n.org/comp/alpha/hct/graphics.html

2.
On rare occasions, RAMDAC setting is failure.
https://twitter.com/nullnilaki/status/511317173977903104/photo/1
I think that Gloria Synergy's bios and SRM are not a well-matched.
See:
Graphic Card Compatibility List
http://moon.hanya-n.org/comp/alpha/hct/graphics.html



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