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port-arm/47156: ETTF doesn't work
>Number: 47156
>Category: port-arm
>Synopsis: ETTF doesn't work
>Confidential: no
>Severity: serious
>Priority: medium
>Responsible: port-arm-maintainer
>State: open
>Class: sw-bug
>Submitter-Id: net
>Arrival-Date: Sat Nov 03 15:00:00 +0000 2012
>Originator: hashimoto kenichi
>Release: 6.99.14
>Organization:
Genetec Corp.
>Environment:
MACHINE: evbarm
MACHINE_ARCH: arm
Building kernel: NETWALKER
>Description:
USB keyboard doesn't work in evbarm/NetWalker.
I think that is wrong bit assignment of EHCI_PS_PSPD.
http://mail-index.netbsd.org/tech-kern/2010/09/09/msg008833.html
However, in the EHCI specification, this bit has been designated as reserve.
I have confirmed by i.MX series (Freescale) only.
>How-To-Repeat:
Built-in USB Keyboard doesn't work, always.
>Fix:
Patch
diff --git a/sys/arch/arm/imx/imxusb.c b/sys/arch/arm/imx/imxusb.c
--- a/sys/arch/arm/imx/imxusb.c
+++ b/sys/arch/arm/imx/imxusb.c
@@ -94,6 +94,8 @@
sc->sc_usbc = usbc;
hsc->sc_bus.hci_private = sc;
+ sc->sc_hsc.sc_flags = EHCIF_ETTF;
+
aprint_normal("\n");
/* per unit registers */
diff --git a/sys/dev/usb/ehci.c b/sys/dev/usb/ehci.c
--- a/sys/dev/usb/ehci.c
+++ b/sys/dev/usb/ehci.c
@@ -2362,8 +2362,6 @@
v = EOREAD4(sc, EHCI_PORTSC(index));
DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v));
- i = UPS_HIGH_SPEED;
-#if 0
if (sc->sc_flags & EHCIF_ETTF) {
/*
* If we are doing embedded transaction translation,
@@ -2372,8 +2370,10 @@
* the same way as in USBSTATUS.
*/
i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED;
+ } else {
+ i = UPS_HIGH_SPEED;
}
-#endif
+
if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
diff --git a/sys/dev/usb/ehcireg.h b/sys/dev/usb/ehcireg.h
--- a/sys/dev/usb/ehcireg.h
+++ b/sys/dev/usb/ehcireg.h
@@ -149,10 +149,10 @@
#define EHCI_CONF_CF 0x00000001 /* RW configure flag */
#define EHCI_PORTSC(n) (0x40+4*(n)) /* RO, RW, RWC Port Status reg */
-#define EHCI_PS_PSPD 0x03000000 /* RO port speed (ETTF) */
+#define EHCI_PS_PSPD 0x0c000000 /* RO port speed (ETTF) */
#define EHCI_PS_PSPD_FS 0x00000000 /* Full speed (ETTF) */
-#define EHCI_PS_PSPD_LS 0x01000000 /* Low speed (ETTF) */
-#define EHCI_PS_PSPD_HS 0x02000000 /* High speed (ETTF) */
+#define EHCI_PS_PSPD_LS 0x04000000 /* Low speed (ETTF) */
+#define EHCI_PS_PSPD_HS 0x08000000 /* High speed (ETTF) */
#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current
ena */
#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */
#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */
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