Re: toolchain/45439: gcc generates out-of-range branch insn for m68k

[Hauke Fath <hauke%Espresso.Rhein-Neckar.DE@localhost>]

The following reply was made to PR toolchain/45439; it has been noted by GNATS.

From: Hauke Fath <hauke%Espresso.Rhein-Neckar.DE@localhost>
To: gnats-bugs%NetBSD.org@localhost
Cc: toolchain-manager%NetBSD.org@localhost, gnats-admin%NetBSD.org@localhost
Subject: Re: toolchain/45439: gcc generates out-of-range branch insn for
 m68k
Date: Fri, 7 Oct 2011 21:18:52 +0200

 At 18:20 Uhr +0000 7.10.2011, David Laight wrote:
 > Possibly this is an assembler bug.
 > The 68k coprocesser conditional branches can have either a 16bit
 > or 32bit signed offset.
 >
 > The compiler could add an explicit .l suffix, but I don't expect
 > that it expects to - and probably doesn't for non-coprocessor
 > branches.
 
 The as(1) info documentation has a paragraph about the magic it works to
 pick the proper displacement for branch insns, to the point where it will
 insert a jmp for a bra if needs be. The corresponding paragraph on fpu
 branches is way shorter:
 
      Each of these pseudo-operations always expands to a single Motorola
      coprocessor branch instruction, word or long.  All Motorola
      coprocessor branch instructions allow both word and long
      displacements.
 
 So gcc grew to expect a smart assembler, and gas is dragging its feet?
 
        hauke
 
 --
 "It's never straight up and down"     (DEVO)