Re: port-i386/44581: MacBook1,1 won't resume after suspend

[Taylor R Campbell <campbell+netbsd%mumble.net@localhost>]

The following reply was made to PR port-i386/44581; it has been noted by GNATS.

From: Taylor R Campbell <campbell+netbsd%mumble.net@localhost>
To: gnats-bugs%NetBSD.org@localhost
Cc: 
Subject: Re: port-i386/44581: MacBook1,1 won't resume after suspend
Date: Wed, 16 Feb 2011 20:19:10 +0000

 fwohci(4) is not happy to attach if its PCI command status register
 does not have bus mastering or memory mapping enabled.  I think this
 is the case for many drivers.  If I have fwohci0 detached, I observe
 that when pci3 is resumed, device 3 function 0 (where fwohci0
 attaches) has its command status register zeroed.  That makes
 fwohci_pci_attach fail, because pci_mapreg_map thinks the flags are
 inappropriate.
 
 I tried the following patch, and, lo and behold, the machine resumes!
 (I have lots of changes in this tree which may be necessary too.)
 
 But here's the weird part.  The output I see is
 
    fwohci0: on resume, csr = 42992150
    fwohci0: setting csr to 42992150
 
 I'm glad my machine is resuming now, but this leaves me unsatisfied
 inside...
 
 Also, if I detach fwohci0 before suspending and rescan pci3 after
 resuming, then the csr has bus mastering and memory mapping disabled,
 so fwohci0 fails to attach.  I know this doesn't matter much, but it
 would be nice if suspending while fwohci0 is detached didn't render
 fwohci0 unusable until the next reboot.
 
 Index: fwohci_pci.c
 ===================================================================
 RCS file: /cvsroot/src/sys/dev/pci/fwohci_pci.c,v
 retrieving revision 1.39
 diff -p -u -r1.39 fwohci_pci.c
 --- fwohci_pci.c       29 Apr 2010 06:41:27 -0000      1.39
 +++ fwohci_pci.c       16 Feb 2011 20:08:21 -0000
 @@ -214,10 +213,18 @@ fwohci_pci_resume(device_t dv, const pmf
  {
        struct fwohci_pci_softc *psc = device_private(dv);
        int s;
 +      uint32_t csr;
  
        s = splbio();
 +      csr = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG);
 +      aprint_normal_dev(dv, "on resume, csr = %d\n", csr);
 +      csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
 +      aprint_normal_dev(dv, "setting csr to %d\n", csr);
 +      pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG, csr);
        fwohci_resume(&psc->psc_sc);
 +      aprint_normal_dev(dv, "fwohci_resume returned, about to splx %d\n", s);
        splx(s);
 +      aprint_normal_dev(dv, "fwohci_resume splx %d\n", s);
  
        return true;
  }