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port-amd64/42861: Correct and add many remain MSR definitions
>Number: 42861
>Category: port-amd64
>Synopsis: Correct and add many remain MSR definitions
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: port-amd64-maintainer
>State: open
>Class: change-request
>Submitter-Id: net
>Arrival-Date: Mon Feb 22 10:05:00 +0000 2010
>Originator: Murray Armfield
>Release: NetBSD-current
>Organization:
N/A
>Environment:
N/A
>Description:
From reading the AMD Architecture Programmers Manual, Volume 2: System
Programming, I've gleaned many additional MSR's and a couple of corrections for
sys/arch/x86/include/specialreg.h. The corrections are to reversed numbering on
the MSR_MC3_xxx and MSR_MC4_xxx and MSR_SYSCFG register is at the wrong
location. None of these definitions have been used in code.
>How-To-Repeat:
Inspection of specialreg.h file and reading doco
>Fix:
diff -Naur NetBSD/sys/arch/x86/include/specialreg.h
NetBSD-patch/sys/arch/x86/include/specialreg.h
--- NetBSD/sys/arch/x86/include/specialreg.h 2010-02-05 09:11:28.000000000
+1100
+++ NetBSD-patch/sys/arch/x86/include/specialreg.h 2010-02-22
20:32:08.891112588 +1100
@@ -298,7 +298,12 @@
#define MSR_SYSENTER_ESP 0x175 /* PII+ only */
#define MSR_SYSENTER_EIP 0x176 /* PII+ only */
#define MSR_MCG_CAP 0x179
+#define MCG_CAP_Count 0x0f /* Number of reporting banks */
+#define MCG_CAP_CTLP 0x10 /* MCG_CTL_PMCG_CTL reg. present */
#define MSR_MCG_STATUS 0x17a
+#define MCG_STATUS_RIPV 0x00000001 /* Restart IP Valid Flag */
+#define MCG_STATUS_EIPV 0x00000002 /* Error IP Valid Flag */
+#define MCG_STATUS_MCIP 0x00000004 /* Machine Check In-Prog. */
#define MSR_MCG_CTL 0x17b
#define MSR_EVNTSEL0 0x186
#define MSR_EVNTSEL1 0x187
@@ -342,6 +347,7 @@
#define MSR_MTRRfix4K_E8000 0x26d
#define MSR_MTRRfix4K_F0000 0x26e
#define MSR_MTRRfix4K_F8000 0x26f
+#define MSR_PAT 0x277
#define MSR_MTRRdefType 0x2ff
#define MSR_MC0_CTL 0x400
#define MSR_MC0_STATUS 0x401
@@ -355,14 +361,39 @@
#define MSR_MC2_STATUS 0x409
#define MSR_MC2_ADDR 0x40a
#define MSR_MC2_MISC 0x40b
-#define MSR_MC4_CTL 0x40c
-#define MSR_MC4_STATUS 0x40d
-#define MSR_MC4_ADDR 0x40e
-#define MSR_MC4_MISC 0x40f
-#define MSR_MC3_CTL 0x410
-#define MSR_MC3_STATUS 0x411
-#define MSR_MC3_ADDR 0x412
-#define MSR_MC3_MISC 0x413
+#define MSR_MC3_CTL 0x40c
+#define MSR_MC3_STATUS 0x40d
+#define MSR_MC3_ADDR 0x40e
+#define MSR_MC3_MISC 0x40f
+#define MSR_MC4_CTL 0x410
+#define MSR_MC4_STATUS 0x411
+#define MSR_MC4_ADDR 0x412
+#define MSR_MC4_MISC 0x413
+#define MSR_MC5_CTL 0x414
+#define MSR_MC5_STATUS 0x415
+#define MSR_MC5_ADDR 0x416
+#define MSR_MC5_MISC 0x417
+
+#define MCi_STAT_MCAErr 0x000000000000ffff /* MCA Error Code */
+#define MCi_STAT_ModErr 0x00000000ffff0000 /* Model-Specific Err
Code */
+#define MCi_STAT_Other 0x01ffffff00000000 /* Other Information */
+#define MCi_STAT_PCC 0x0200000000000000 /* Proc.-Context
Corrupt */
+#define MCi_STAT_ADDRV 0x0400000000000000 /* Error-Addr. Reg.
Valid */
+#define MCi_STAT_MISCV 0x0800000000000000 /* Misc-Error Reg.
Valid */
+#define MCi_STAT_EN 0x1000000000000000 /* Error Condition
Enabled */
+#define MCi_STAT_UC 0x2000000000000000 /* Uncorrected Error */
+#define MCi_STAT_OVER 0x4000000000000000 /* Status Register
Overflow */
+#define MCi_STAT_VAL 0x8000000000000000 /* Valid */
+
+#define MCi_MISC_BLKP 0x00000000ff000000 /* Blk ptr to more MISC
reg */
+#define MCi_MISC_ERRCT 0x0000ffff00000000 /* Error Counter */
+#define MCi_MISC_OF 0x0001000000000000 /* Overflow */
+#define MCi_MISC_INTT 0x0006000000000000 /* Interrupt Type */
+#define MCi_MISC_CNTE 0x0008000000000000 /* Counter Enable */
+#define MCi_MISC_LVTOFF 0x00f0000000000000 /* LVT Offset */
+#define MCi_MISC_LKD 0x2000000000000000 /* Locked */
+#define MCi_MISC_CTRP 0x4000000000000000 /* Counter Present */
+#define MCi_MISC_VAL 0x8000000000000000 /* Valid */
/*
* VIA "Nehemiah" MSRs
@@ -392,30 +423,82 @@
/*
* AMD K8 (Opteron) MSRs.
*/
-#define MSR_SYSCFG 0xc0000010
-
-#define MSR_EFER 0xc0000080 /* Extended feature enable */
-#define EFER_SCE 0x00000001 /* SYSCALL extension */
-#define EFER_LME 0x00000100 /* Long Mode Active */
-#define EFER_LMA 0x00000400 /* Long Mode
Enabled */
-#define EFER_NXE 0x00000800 /* No-Execute Enabled */
-
-#define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */
-#define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */
-#define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */
-#define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */
-
-#define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */
-#define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */
-#define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */
-
+#define MSR_EFER 0xc0000080 /* Extended feature enable */
+#define EFER_SCE 0x00000001 /* SYSCALL extension */
+#define EFER_LME 0x00000100 /* Long Mode Enabled */
+#define EFER_LMA 0x00000400 /* Long Mode Active */
+#define EFER_NXE 0x00000800 /* No-Execute Enabled */
+#define EFER_SVME 0x00001000 /* Secure Virtual
Machine Enabled */
+#define EFER_LMSLE 0x00002000 /* Long Mode Segment
Limit Enabled */
+#define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR
Enabled */
+
+#define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */
+#define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */
+#define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */
+#define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */
+
+#define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */
+#define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */
+#define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */
+#define MSR_TSCAUX 0xc0000103 /* RDTSCP instruction */
+
+#define MSR_MC4MISC1 0xc0000408 /* Machine Check error info 1 */
+#define MSR_MC4MISC2 0xc0000409 /* Machine Check error info 2 */
+#define MSR_MC4MISC3 0xc000040A /* Machine Check error info 3 */
+
+#define MSR_SYSCFG 0xc0010010 /* System-configuration Register */
+#define SYSCFG_MFDE 0x00040000 /* MtrrFixDramEn */
+#define SYSCFG_MFDM 0x00080000 /* MtrrFixDramModEn */
+#define SYSCFG_MVDM 0x00100000 /* MtrrVarDramEn */
+#define SYSCFG_TOM2 0x00200000 /* MtrrTom2En */
+
+#define MSR_IORRBase0 0xc0010016 /* IORRs */
+#define MSR_IORRMask0 0xc0010017
+#define MSR_IORRBase1 0xc0010018
+#define MSR_IORRMask1 0xc0010019
+
+#define MSR_TOP_MEM 0xc001001a /* Top Of Memory */
+#define MSR_TOP_MEM2 0xc001001d
+
+#define MSR_PRONAME0 0xc0010030 /* Processor_Name_String */
+#define MSR_PRONAME1 0xc0010031
+#define MSR_PRONAME2 0xc0010032
+#define MSR_PRONAME3 0xc0010033
+#define MSR_PRONAME4 0xc0010034
+#define MSR_PRONAME5 0xc0010035
+
+#define MSR_PSTATECURLIM 0xc0010061 /* Hardware P-State Control */
+#define MSR_PSTATECONTROL 0xc0010062
+#define MSR_PSTATESTATUS 0xc0010063
+
+#define MSR_CPUWTCHDOGTMR 0xc0010074 /* CPU Watchdog Timer Register
*/
+#define CPUWDTMR_EN 0x00000001 /* Enable */
+#define CPUWDTMR_TB 0x00000006 /* Time Base */
+#define CPUWDTMR_CS 0x00000078 /* Count Select */
+
+#define MSR_SMBASE 0xc0010111 /* SMBASE Register */
+#define MSR_SMMADDR 0xc0010112 /* SMRAM Protected Area */
+#define MSR_SMMMASK 0xc0010113 /* SMRAM Protected Area */
#define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */
-#define VMCR_DPD 0x00000001 /* Debug port disable */
+#define VMCR_DPD 0x00000001 /* Debug port disable */
#define VMCR_RINIT 0x00000002 /* intercept init */
#define VMCR_DISA20 0x00000004 /* Disable A20 masking
*/
#define VMCR_LOCK 0x00000008 /* SVM Lock */
#define VMCR_SVMED 0x00000010 /* SVME Disable */
-#define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */
+#define MSR_IGNNE 0xc0010115 /* Sets proc IGNNE signal */
+#define MSR_SMM_CTL 0xc0010116 /* SVM Related MSRs */
+#define SMM_DISMISS 0x01 /* Clear SMI pending flag */
+#define SMM_ENTER 0x02 /* Enter SMM */
+#define SMM_SMICYCLE 0x04 /* Send SMI special cycle */
+#define SMM_EXIT 0x08 /* Exit SMM */
+#define SMM_RSMCYCLE 0x10 /* Send RSM special cycle */
+#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM Related MSRs */
+#define MSR_SVM_KEY_MSR 0xc0010118 /* SVM Lock */
+#define MSR_SMM_KEY_MSR 0xc0010119 /* SMM Lock */
+#define MSR_LOC_SMI_ST 0xc001011a /* Local SMI Status */
+#define MSR_SMI_TRG_IO 0xc0010056 /* SMI_Trigger_IO_Cycle */
+#define MSR_OSVW_ID_LEN 0xc0010140 /* OSVW_ID_Length */
+#define MSR_OSVM_STATUS 0xc0010141 /* OSVM Status */
/*
* These require a 'passcode' for access. See cpufunc.h.
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