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Re: port-sgimips/38932: sgimips bus_dmamap_sync() is incorrect

On Tue, Jun 10, 2008 at 07:35:02PM +0000, Izumi Tsutsui wrote:
> The following reply was made to PR port-sgimips/38932; it has been noted by 
> From: Izumi Tsutsui <>
> To:
> Cc:, 
> Subject: Re: port-sgimips/38932: sgimips bus_dmamap_sync() is incorrect
> Date: Wed, 11 Jun 2008 04:31:35 +0900
>  >    bus_dmamap_sync(POSTREAD) should do a cache invalidation.
>  >    bus_dmamap_sync(PREREAD) should probably be turned to a NOP
>  No, it won't work if specified region isn't cacheline aligned.
>  We can't invalidate cache if specified region is not cacheline aligned
>  (otherwise some necessary data in the same cacheline could be lost) and
>  we have to use writeback and invalidate in that case, but
>  such writeback should be done _before_ starting DMA otherwise
>  transfered data via DMA will be lost by writeback.
>  That's the reason why all POSTWRITE and POSTREAD are no-op.
>  Drivers should call PREREAD after each polling instead.
>  (see sys/dev/ic/rtl8169.c:re_rxeof() etc.)

I see your point. But I'm not sure such devices can work reliably
with a write-back cache if regions are not cacheline-aligned.
For example, I'm almost sure an uchi/ehci can't work reliably on hosts
with write-back caches (unless the descriptors are mappped uncached).
I suspect re(4) has the same issue with re_desc->re_cmdstat (the updated
re_cmdstat from a descriptor may be lost if the host writes another
descriptor in the same cache line).

Manuel Bouyer <>
     NetBSD: 26 ans d'experience feront toujours la difference

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