bin/38723: Additional AMD PowerNow status bits for Family 10h processors

[paul%whooppee.com@localhost]

>Number:         38723
>Category:       bin
>Synopsis:       Additional AMD PowerNow status bits for Family 10h processors
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    bin-bug-people
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Wed May 21 18:00:00 +0000 2008
>Originator:     Paul Goyette
>Release:        NetBSD 4.99.62
>Organization:
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>Environment:
        
        
System: NetBSD quicky.whooppee.com 4.99.62 NetBSD 4.99.62 (QUICKY (ASUS M2N32 
WS) 2008-05-14 13:20:42) #1: Wed May 14 06:25:08 PDT 2008 
paul%speedy.whooppee.com@localhost:/build/obj/amd64/sys/arch/amd64/compile/QUICKY
 amd64
Architecture: x86_64
Machine: amd64
>Description:
        According to AMD document # 25481, page 19, there are some
        additional bits in the Advanced Power Management Information
        beyond those which are currently decoded by the cpuctl utility 
        (usr.sbin/cpuctl/arch/i386.c).

        This is really not serious, except that when these extra bits
        are set, it prevents the bitmask_snprintf() from decoding any
        additional bits!

        From the quoted AMD document:
        EDX     8       TscInvariant. 1 = The TSC rate is ensured to be
                        invariant across all P-States, C-States, and stop
                        grant transitions (such as STPCLK Throttling);
                        therefore the TSC is suitable for use as a source 
                        of time. 0 = No such guarantee is made and software
                        should avoid attempting to use the TSC as a source
                        of time.
        EDX     7       HwPState. Hardware P-State control. [The P-State
                        Current Limit Register] MSRC001_0061, [The P-State
                        Control Register] MSRC001_0062, and [The P-State
                        Status Register] MSRC001_0063 exist.
        EDX     6       100MhzSteps: 100 Mhz multiplier control.

        
>How-To-Repeat:
        Run /usr/sbin/cpuctl on a processor with these additional bits 
        set and you get null output!
        
>Fix:
The following patch defines these additional bits.
        
Index: src/usr.sbin/cpuctl/arch/i386.c
===================================================================
RCS file: /cvsroot/src/usr.sbin/cpuctl/arch/i386.c,v
retrieving revision 1.5
diff -u -p -r1.5 i386.c
--- i386.c      21 May 2008 01:12:12 -0000      1.5
+++ i386.c      21 May 2008 17:52:59 -0000
@@ -1936,7 +1936,8 @@ powernow_probe(struct cpu_info *ci)
                return;
        x86_cpuid(0x80000007, regs);
 
-       bitmask_snprintf(regs[3], "\20\6STC\5TM\4TTP\3VID\2FID\1TS", line,
+       bitmask_snprintf(regs[3], "\20\9TscInv\8HwPState\7100MHz"
+                                 "\6STC\5TM\4TTP\3VID\2FID\1TS", line,
            sizeof(line));
        aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n",
            line);

>Unformatted: