Pierre Pronchery wrote:
> Generally speaking, the amd64 port's default kernel is not very friendly
> to laptops. Enhanced Speedstep in particular is not supported for Intel
> machines featuring this instruction set (eg Core 2 Duo "Merom").

I forgot to include this, in case it helps.

sysctl -a | grep est:
machdep.est.frequency.target = 1000
machdep.est.frequency.current = 1000
machdep.est.frequency.available = 2000 1000

estd -f:
Supported frequencies (Enhanced SpeedStep Mode):
1000 MHz
2000 MHz

dmesg excerpt:
NetBSD 4.0_BETA2 (GENERIC.MP) #26: Tue Jul 10 14:44:16 CEST 2007
khorben@syn.defora.rom:/usr/obj/sys/arch/amd64/compile/GENERIC.MP
total memory = 2046 MB
avail memory = 1961 MB
timecounter: Timecounters tick every 10.000 msec
timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
mainbus0 (root)
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Core(TM)2 CPU         T7200  @ 2.00GHz, 1995.20 MHz
cpu0: features: bffbfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features: bffbfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,B20,DS,ACPI,MMX>
cpu0: features: bffbfbff<FXSR,SSE,SSE2,SS,HTT,TM,SBF>
cpu0: features2: e3bd<SSE3,MONITOR,DS-CPL,VMX,EST,TM2,xTPR>
cpu0: features3: bffbfbff<SYSCALL/SYSRET,XD,EM64T>
cpu0: L2 cache 4 MB 64B/line 16-way
cpu0: probing Enhanced SpeedStep
cpu0: Enhanced SpeedStep (1324 mV) 2000 MHz
cpu0: unknown Enhanced SpeedStep CPU.
cpu0: using only highest and lowest power states.
cpu0: Enhanced SpeedStep frequencies available (MHz): 2000 1000
cpu0: calibrating local timer
cpu0: apic clock running at 166 MHz
cpu0: 64 page colors
cpu1 at mainbus0: apid 1 (application processor)
cpu1: starting
cpu1: Intel(R) Core(TM)2 CPU         T7200  @ 2.00GHz, 1995.01 MHz
cpu1: features: bffbfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu1: features: bffbfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,B20,DS,ACPI,MMX>
cpu1: features: bffbfbff<FXSR,SSE,SSE2,SS,HTT,TM,SBF>
cpu1: features2: e3bd<SSE3,MONITOR,DS-CPL,VMX,EST,TM2,xTPR>
cpu1: features3: bffbfbff<SYSCALL/SYSRET,XD,EM64T>
cpu1: L2 cache 4 MB 64B/line 16-way
cpu1: probing Enhanced SpeedStep

-- 
khorben