Subject: Re: port-evbmips/31992: alchemy ICU is too Au1000 specific
To: Simon Burge <simonb@wasabisystems.com>
From: Garrett D'Amore <garrett_damore@tadpole.com>
List: netbsd-bugs
Date: 11/10/2005 17:02:46
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Attached find my latest changes, which provides processor specific
source files with irq name tables and also the aubus mappings. Kernels
can be built for specific CPUs using the new config directives:
ALCHEMY_AU1000
ALCHEMY_AU1100
ALCHEMY_AU1500
ALCHEMY_AU1550
The current PB1000 config file defines all of these, and continues to
function properly on any of them. (I'm not renaming PB1000 yet, see below.)
I only have a DBAu1500 and DBAu1550 boards, but I have verified that
these changes work on both of those boards.
I have commented out peripherals for which we don't have any driver
support in the aubus maps, for now.
Note that similiar work for the *boards* (as opposed to processors)
should also be done, but I don't want to wait for this to get this
change committed. Once I have the changes for the *board* support done
as well, then I'll file another PR, and at that time I'll probably
rename the PB1000 file to ALCHEMY as well. (And maybe supply truly
board-specific config files as well.)
Anyway, without further ado, here are the changes...
-- Garrett
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? sys/arch/evbmips/compile/obj
Index: sys/arch/evbmips/conf/PB1000
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/evbmips/conf/PB1000,v
retrieving revision 1.1.1.1.6.1
diff -u -r1.1.1.1.6.1 PB1000
--- sys/arch/evbmips/conf/PB1000 10 Nov 2005 08:39:47 -0000 1.1.1.1.6.1
+++ sys/arch/evbmips/conf/PB1000 11 Nov 2005 00:54:38 -0000
@@ -1,7 +1,6 @@
# $NetBSD: PB1000,v 1.25 2005/08/19 05:19:50 christos Exp $
#
-# Kernel config for the Alchemy Semiconductor (AMD) PB1000, PB1500,
-# DBAu1000 and DBAu1500 evaluation boards.
+# Kernel config for the AMD Alchemy PB1XXX and DB1XXX evaluation boards.
include "arch/evbmips/conf/std.pb1000"
@@ -15,6 +14,11 @@
options CONSPEED=115200 # YAMON default
options HZ=512 # for profiling
+options ALCHEMY_AU1000
+options ALCHEMY_AU1100
+options ALCHEMY_AU1500
+options ALCHEMY_AU1550
+
#options LOCKDEBUG
options SOSEND_LOAN
options SOSEND_COUNTERS
Index: sys/arch/mips/alchemy/au1000_chipdep.c
===================================================================
RCS file: sys/arch/mips/alchemy/au1000_chipdep.c
diff -N sys/arch/mips/alchemy/au1000_chipdep.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sys/arch/mips/alchemy/au1000_chipdep.c 11 Nov 2005 00:54:42 -0000
@@ -0,0 +1,146 @@
+/* $NetBSD$ */
+
+/*-
+ * Copyright (c) 2005 Tadpole Computer Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Tadpole Computer Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Tadpole Computer Inc. may not be used to endorse
+ * or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <machine/bus.h>
+#include <machine/locore.h>
+#include <mips/alchemy/include/aureg.h>
+#include <mips/alchemy/include/auvar.h>
+
+static const char *au1000_irqnames[] = {
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "ssi0",
+ "ssi1",
+ "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "toy tick",
+ "toy match0",
+ "toy match1",
+ "toy match2",
+ "rtc tick",
+ "rtc match0",
+ "rtc match1",
+ "rtc match2",
+ "irda tx",
+ "irda rx",
+ "usb intr",
+ "usb suspend",
+ "usb host",
+ "ac97",
+ "mac0",
+ "mac1",
+ "irq 30",
+ "ac97 cmd",
+ "gpio 0",
+ "gpio 1",
+ "gpio 2",
+ "gpio 3",
+ "gpio 4",
+ "gpio 5",
+ "gpio 6",
+ "gpio 7",
+ "gpio 8",
+ "gpio 9",
+ "gpio 10",
+ "gpio 11",
+ "gpio 12",
+ "gpio 13",
+ "gpio 14",
+ "gpio 15",
+ "gpio 16",
+ "gpio 17",
+ "gpio 18",
+ "gpio 19",
+ "gpio 20",
+ "gpio 21",
+ "gpio 22",
+ "gpio 23",
+ "gpio 24",
+ "gpio 25",
+ "gpio 26",
+ "gpio 27",
+ "gpio 28",
+ "gpio 29",
+ "gpio 30",
+ "gpio 31"
+};
+
+static au_dev_t au1000_devices[] = {
+ { "aucom", { UART0_BASE }, { 0, -1 }},
+ { "aucom", { UART1_BASE }, { 1, -1 }},
+ { "aucom", { UART2_BASE }, { 2, -1 }},
+ { "aucom", { UART3_BASE }, { 3, -1 }},
+ { "aurtc", { }, { -1, -1 }},
+ { "aumac", { MAC0_BASE, MAC0_ENABLE, MAC0_DMA_BASE }, { 28, -1 }},
+ { "aumac", { MAC1_BASE, MAC1_ENABLE, MAC1_DMA_BASE }, { 28, -1 }},
+ { "ohci", { USBH_BASE, USBH_ENABLE, USBH_SIZE }, { 26, -1 }},
+#if 0
+ { "auaudio", { AC97_BASE }, { 27, 31 }},
+ { "i2s", { I2S_BASE }, { 30, -1 }},
+ { "ssi", { SSI0_BASE }, { 4, -1 }},
+ { "ssi", { SSI1_BASE }, { 5, -1 }},
+ { "usbd", { USBD_BASE }, { 24, 25 }},
+ { "irda", { IRDA_BASE }, { 22, 23 }},
+ { "gpio", { SYS_BASE }, { -1, -1 }},
+ { "gpio", { GPIO2_BASE }, { -1, -1 }},
+ /* XXX: lcd? */
+#endif
+ { NULL }
+};
+
+static au_chipdep_t au1000_chipdep = {
+ "au1000",
+ { IC0_BASE, IC1_BASE }, /* ICUs */
+ au1000_devices,
+ au1000_irqnames,
+};
+
+boolean_t
+au1000_match(au_chipdep_t **cpp)
+{
+
+ if (MIPS_PRID_COPTS(cpu_id) == MIPS_AU1000) {
+ *cpp = &au1000_chipdep;
+ return TRUE;
+ }
+ return FALSE;
+}
Index: sys/arch/mips/alchemy/au1100_chipdep.c
===================================================================
RCS file: sys/arch/mips/alchemy/au1100_chipdep.c
diff -N sys/arch/mips/alchemy/au1100_chipdep.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sys/arch/mips/alchemy/au1100_chipdep.c 11 Nov 2005 00:54:42 -0000
@@ -0,0 +1,146 @@
+/* $NetBSD$ */
+
+/*-
+ * Copyright (c) 2005 Tadpole Computer Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Tadpole Computer Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Tadpole Computer Inc. may not be used to endorse
+ * or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <machine/bus.h>
+#include <machine/locore.h>
+#include <mips/alchemy/include/aureg.h>
+#include <mips/alchemy/include/auvar.h>
+
+static const char *au1100_irqnames[] = {
+ "uart0",
+ "uart1",
+ "sdcard",
+ "uart3",
+ "ssi0",
+ "ssi1",
+ "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "toy tick",
+ "toy match0",
+ "toy match1",
+ "toy match2",
+ "rtc tick",
+ "rtc match0",
+ "rtc match1",
+ "rtc match2",
+ "irda tx",
+ "irda rx",
+ "usb intr",
+ "usb suspend",
+ "usb host",
+ "ac97",
+ "mac0",
+ "gpio 208:215",
+ "lcd",
+ "ac97 cmd",
+ "gpio 0",
+ "gpio 1",
+ "gpio 2",
+ "gpio 3",
+ "gpio 4",
+ "gpio 5",
+ "gpio 6",
+ "gpio 7",
+ "gpio 8",
+ "gpio 9",
+ "gpio 10",
+ "gpio 11",
+ "gpio 12",
+ "gpio 13",
+ "gpio 14",
+ "gpio 15",
+ "gpio 16",
+ "gpio 17",
+ "gpio 18",
+ "gpio 19",
+ "gpio 20",
+ "gpio 21",
+ "gpio 22",
+ "gpio 23",
+ "gpio 24",
+ "gpio 25",
+ "gpio 26",
+ "gpio 27",
+ "gpio 28",
+ "gpio 29",
+ "gpio 30",
+ "gpio 31"
+};
+
+static au_dev_t au1100_devices[] = {
+ { "aucom", { UART0_BASE }, { 0, -1 }},
+ { "aucom", { UART1_BASE }, { 1, -1 }},
+ { "aucom", { UART3_BASE }, { 3, -1 }},
+ { "aurtc", { }, { -1, -1 }},
+ { "aumac", { MAC0_BASE, MAC0_ENABLE, MAC0_DMA_BASE }, { 28, -1 }},
+ { "ohci", { USBH_BASE, USBH_ENABLE, USBH_SIZE }, { 26, -1 }},
+#if 0
+ { "auaudio", { AC97_BASE }, { 27, 31 }},
+ { "sdcard", { SD0_BASE }, { 2, -1 }},
+ { "sdcard", { SD1_BASE }, { 2, -1 }},
+ { "i2s", { I2S_BASE }, { 30, -1 }},
+ { "ssi", { SSI0_BASE }, { 4, -1 }},
+ { "ssi", { SSI1_BASE }, { 5, -1 }},
+ { "usbd", { USBD_BASE }, { 24, 25 }},
+ { "irda", { IRDA_BASE }, { 22, 23 }},
+ { "gpio", { SYS_BASE }, { -1, -1 }},
+ { "gpio", { GPIO2_BASE }, { -1, -1 }},
+ /* XXX: lcd? */
+#endif
+ { NULL }
+};
+
+static au_chipdep_t au1100_chipdep = {
+ "au1100",
+ { IC0_BASE, IC1_BASE }, /* ICUs */
+ au1100_devices,
+ au1100_irqnames,
+};
+
+boolean_t
+au1100_match(au_chipdep_t **cpp)
+{
+
+ if (MIPS_PRID_COPTS(cpu_id) == MIPS_AU1100) {
+ *cpp = &au1100_chipdep;
+ return TRUE;
+ }
+ return FALSE;
+}
Index: sys/arch/mips/alchemy/au1500_chipdep.c
===================================================================
RCS file: sys/arch/mips/alchemy/au1500_chipdep.c
diff -N sys/arch/mips/alchemy/au1500_chipdep.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sys/arch/mips/alchemy/au1500_chipdep.c 11 Nov 2005 00:54:42 -0000
@@ -0,0 +1,142 @@
+/* $NetBSD$ */
+
+/*-
+ * Copyright (c) 2005 Tadpole Computer Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Tadpole Computer Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Tadpole Computer Inc. may not be used to endorse
+ * or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <machine/bus.h>
+#include <machine/locore.h>
+#include <mips/alchemy/include/aureg.h>
+#include <mips/alchemy/include/auvar.h>
+
+static const char *au1500_irqnames[] = {
+ "uart0",
+ "pci inta",
+ "pci intb",
+ "uart3",
+ "pci intc",
+ "pci intd",
+ "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "toy tick",
+ "toy match0",
+ "toy match1",
+ "toy match2",
+ "rtc tick",
+ "rtc match0",
+ "rtc match1",
+ "rtc match2",
+ "pci error",
+ "irq 23",
+ "usb intr",
+ "usb suspend",
+ "usb host",
+ "ac97",
+ "mac0",
+ "mac1",
+ "irq 30",
+ "ac97 cmd",
+ "gpio 0",
+ "gpio 1",
+ "gpio 2",
+ "gpio 3",
+ "gpio 4",
+ "gpio 5",
+ "gpio 6",
+ "gpio 7",
+ "gpio 8",
+ "gpio 9",
+ "gpio 10",
+ "gpio 11",
+ "gpio 12",
+ "gpio 13",
+ "gpio 14",
+ "gpio 15",
+ "gpio 200",
+ "gpio 201",
+ "gpio 202",
+ "gpio 203",
+ "gpio 20",
+ "gpio 204",
+ "gpio 205",
+ "gpio 23",
+ "gpio 24",
+ "gpio 25",
+ "gpio 26",
+ "gpio 27",
+ "gpio 28",
+ "gpio 206",
+ "gpio 207",
+ "gpio 208:215"
+};
+
+static au_dev_t au1500_devices[] = {
+ { "aucom", { UART0_BASE }, { 0, -1 }},
+ { "aucom", { UART3_BASE }, { 3, -1 }},
+ { "aurtc", { }, { -1, -1 }},
+ { "aumac", { AU1500_MAC0_BASE, AU1500_MAC0_ENABLE,
+ MAC0_DMA_BASE }, { 28, -1 }},
+ { "aumac", { AU1500_MAC1_BASE, AU1500_MAC1_ENABLE,
+ MAC1_DMA_BASE }, { 29, -1 }},
+ { "ohci", { USBH_BASE, USBH_ENABLE, USBH_SIZE }, { 26, -1 }},
+#if 0
+ { "auaudio", { AC97_BASE }, { 27, 31 }},
+ { "usbd", { USBD_BASE }, { 24, 25 }},
+ { "gpio", { SYS_BASE }, { -1, -1 }},
+ { "gpio", { GPIO2_BASE }, { -1, -1 }},
+ { "aupci", { PCI_BASE }, { -1, -1 }},
+#endif
+ { NULL }
+};
+
+static au_chipdep_t au1500_chipdep = {
+ "au1500",
+ { IC0_BASE, IC1_BASE }, /* ICUs */
+ au1500_devices,
+ au1500_irqnames,
+};
+
+boolean_t
+au1500_match(au_chipdep_t **cpp)
+{
+
+ if (MIPS_PRID_COPTS(cpu_id) == MIPS_AU1500) {
+ *cpp = &au1500_chipdep;
+ return TRUE;
+ }
+ return FALSE;
+}
Index: sys/arch/mips/alchemy/au1550_chipdep.c
===================================================================
RCS file: sys/arch/mips/alchemy/au1550_chipdep.c
diff -N sys/arch/mips/alchemy/au1550_chipdep.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sys/arch/mips/alchemy/au1550_chipdep.c 11 Nov 2005 00:54:42 -0000
@@ -0,0 +1,146 @@
+/* $NetBSD$ */
+
+/*-
+ * Copyright (c) 2005 Tadpole Computer Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Tadpole Computer Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Tadpole Computer Inc. may not be used to endorse
+ * or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <machine/bus.h>
+#include <machine/locore.h>
+#include <mips/alchemy/include/aureg.h>
+#include <mips/alchemy/include/auvar.h>
+
+static const char *au1550_irqnames[] = {
+ "uart0",
+ "pci inta",
+ "pci intb",
+ "ddma",
+ "crypto",
+ "pci intc",
+ "pci intd",
+ "pci reset",
+ "uart1",
+ "uart3",
+ "psc0",
+ "psc1",
+ "psc2",
+ "psc3",
+ "toy tick",
+ "toy match0",
+ "toy match1",
+ "toy match2",
+ "rtc tick",
+ "rtc match0",
+ "rtc match1",
+ "rtc match2",
+ "pci error",
+ "nand",
+ "usb intr",
+ "usb suspend",
+ "usb host",
+ "mac0",
+ "mac1",
+ "irq 29",
+ "irq 30",
+ "irq 31",
+ "gpio 0",
+ "gpio 1",
+ "gpio 2",
+ "gpio 3",
+ "gpio 4",
+ "gpio 5",
+ "gpio 6",
+ "gpio 7",
+ "gpio 8",
+ "gpio 9",
+ "gpio 10",
+ "gpio 11",
+ "gpio 12",
+ "gpio 13",
+ "gpio 14",
+ "gpio 15",
+ "gpio 200",
+ "gpio 201:205",
+ "gpio 16",
+ "gpio 17",
+ "gpio 20",
+ "gpio 21",
+ "gpio 22",
+ "gpio 23",
+ "gpio 24",
+ "gpio 25",
+ "gpio 26",
+ "gpio 27",
+ "gpio 28",
+ "gpio 206",
+ "gpio 207",
+ "gpio 208:215"
+};
+
+static au_dev_t au1550_devices[] = {
+ { "aucom", { UART0_BASE }, { 0, -1 }},
+ { "aucom", { UART1_BASE }, { 8, -1 }},
+ { "aucom", { UART3_BASE }, { 9, -1 }},
+ { "aurtc", { }, { -1, -1 }},
+ { "aumac", { MAC0_BASE, MAC0_ENABLE, MAC0_DMA_BASE }, { 27, -1 }},
+ { "aumac", { MAC1_BASE, MAC1_ENABLE, MAC1_DMA_BASE }, { 28, -1 }},
+ { "ohci", { AU1550_USBH_BASE, AU1550_USBH_ENABLE,
+ AU1550_USBH_SIZE }, { 26, -1 }},
+#if 0
+ { "usbd", { USBD_BASE }, { 24, 25 }},
+ { "aupsc", { PSC0_BASE }, { 10, -1 }},
+ { "aupsc", { PSC1_BASE }, { 11, -1 }},
+ { "aupsc", { PSC2_BASE }, { 12, -1 }},
+ { "aupsc", { PSC3_BASE }, { 13, -1 }},
+ { "gpio", { SYS_BASE }, { -1, -1 }},
+ { "gpio", { GPIO2_BASE }, { -1, -1 }},
+ { "aupci", { PCI_BASE }, { -1, -1 }},
+ { "aucrypto", { CRYPTO_BASE }, { 4, -1 }},
+#endif
+ { NULL }
+};
+
+static au_chipdep_t au1550_chipdep = {
+ "au1550",
+ { IC0_BASE, IC1_BASE }, /* ICUs */
+ au1550_devices,
+ au1550_irqnames,
+};
+
+boolean_t
+au1550_match(au_chipdep_t **cpp)
+{
+
+ if (MIPS_PRID_COPTS(cpu_id) == MIPS_AU1550) {
+ *cpp = &au1550_chipdep;
+ return TRUE;
+ }
+ return FALSE;
+}
Index: sys/arch/mips/alchemy/au_chipdep.c
===================================================================
RCS file: sys/arch/mips/alchemy/au_chipdep.c
diff -N sys/arch/mips/alchemy/au_chipdep.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sys/arch/mips/alchemy/au_chipdep.c 11 Nov 2005 00:54:42 -0000
@@ -0,0 +1,68 @@
+/* $NetBSD$ */
+
+/*-
+ * Copyright (c) 2005 Tadpole Computer Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Tadpole Computer Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Tadpole Computer Inc. may not be used to endorse
+ * or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+#include <sys/param.h>
+#include <machine/bus.h>
+#include <machine/locore.h>
+#include <mips/alchemy/include/aureg.h>
+#include <mips/alchemy/include/auvar.h>
+
+static au_chipdep_t *au_chip = NULL;
+
+au_chipdep_t *
+au_chipdep(void)
+{
+
+ if (au_chip != NULL)
+ return (au_chip);
+
+ if ((au_chip == NULL) &&
+#ifdef ALCHEMY_AU1000
+ (!au1000_match(&au_chip)) &&
+#endif
+#ifdef ALCHEMY_AU1100
+ (!au1100_match(&au_chip)) &&
+#endif
+#ifdef ALCHEMY_AU1500
+ (!au1500_match(&au_chip)) &&
+#endif
+#ifdef ALCHEMY_AU1550
+ (!au1550_match(&au_chip)) &&
+#endif
+ (au_chip == NULL)) {
+ panic("Alchemy SOC %x either not configured or not supported!",
+ cpu_id);
+ }
+ return (au_chip);
+}
Index: sys/arch/mips/alchemy/au_icu.c
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/alchemy/au_icu.c,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 au_icu.c
--- sys/arch/mips/alchemy/au_icu.c 9 Nov 2005 14:17:20 -0000 1.1.1.1
+++ sys/arch/mips/alchemy/au_icu.c 11 Nov 2005 00:54:42 -0000
@@ -116,112 +116,51 @@
#define NIRQS 64
-const char *au1000_intrnames[NIRQS] = {
- "uart0",
- "uart1",
- "uart2",
- "uart3",
- "ssi0",
- "ssi1",
- "dma0",
- "dma1",
- "dma2",
- "dma3",
- "dma4",
- "dma5",
- "dma6",
- "dma7",
- "pc0",
- "pc0 match1",
- "pc0 match2",
- "pc0 match3",
- "pc1",
- "pc1 match1",
- "pc1 match2",
- "pc1 match3",
- "irda tx",
- "irda rx",
- "usb intr",
- "usb suspend",
- "usb host",
- "ac97",
- "mac0",
- "mac1",
- "i2s",
- "ac97 cmd",
-
- "gpio 0",
- "gpio 1",
- "gpio 2",
- "gpio 3",
- "gpio 4",
- "gpio 5",
- "gpio 6",
- "gpio 7",
- "gpio 8",
- "gpio 9",
- "gpio 10",
- "gpio 11",
- "gpio 12",
- "gpio 13",
- "gpio 14",
- "gpio 15",
- "gpio 16",
- "gpio 17",
- "gpio 18",
- "gpio 19",
- "gpio 20",
- "gpio 21",
- "gpio 22",
- "gpio 23",
- "gpio 24",
- "gpio 25",
- "gpio 26",
- "gpio 27",
- "gpio 28",
- "gpio 29",
- "gpio 30",
- "gpio 31",
-};
-
-struct au1000_intrhead {
+struct au_icu_intrhead {
struct evcnt intr_count;
int intr_refcnt;
};
-struct au1000_intrhead au1000_intrtab[NIRQS];
+struct au_icu_intrhead au_icu_intrtab[NIRQS];
#define NINTRS 4 /* MIPS INT0 - INT3 */
-struct au1000_cpuintr {
+struct au_cpuintr {
LIST_HEAD(, evbmips_intrhand) cintr_list;
struct evcnt cintr_count;
};
-struct au1000_cpuintr au1000_cpuintrs[NINTRS];
-const char *au1000_cpuintrnames[NINTRS] = {
+struct au_cpuintr au_cpuintrs[NINTRS];
+const char *au_cpuintrnames[NINTRS] = {
"icu 0, req 0",
"icu 0, req 1",
"icu 1, req 0",
"icu 1, req 1",
};
+static bus_addr_t ic0_base, ic1_base;
+
void
au_intr_init(void)
{
- int i;
+ int i;
+ au_chipdep_t *chip;
for (i = 0; i < NINTRS; i++) {
- LIST_INIT(&au1000_cpuintrs[i].cintr_list);
- evcnt_attach_dynamic(&au1000_cpuintrs[i].cintr_count,
- EVCNT_TYPE_INTR, NULL, "mips", au1000_cpuintrnames[i]);
+ LIST_INIT(&au_cpuintrs[i].cintr_list);
+ evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count,
+ EVCNT_TYPE_INTR, NULL, "mips", au_cpuintrnames[i]);
}
- for (i = 0; i < NIRQS; i++) {
- /* XXX steering - use an irqmap array? */
+ chip = au_chipdep();
+ KASSERT(chip != NULL);
- au1000_intrtab[i].intr_refcnt = 0;
- evcnt_attach_dynamic(&au1000_intrtab[i].intr_count,
- EVCNT_TYPE_INTR, NULL, "au1000", au1000_intrnames[i]);
+ ic0_base = chip->icus[0];
+ ic1_base = chip->icus[1];
+
+ for (i = 0; i < NIRQS; i++) {
+ au_icu_intrtab[i].intr_refcnt = 0;
+ evcnt_attach_dynamic(&au_icu_intrtab[i].intr_count,
+ EVCNT_TYPE_INTR, NULL, chip->name, chip->irqnames[i]);
}
}
@@ -232,6 +171,9 @@
struct evbmips_intrhand *ih;
uint32_t icu_base;
int cpu_int, s;
+ au_chipdep_t *chip;
+
+ chip = au_chipdep();
if (irq >= NIRQS)
panic("au_intr_establish: bogus IRQ %d", irq);
@@ -254,18 +196,18 @@
* a list anyway) per irq, not per CPU interrupt?
*/
cpu_int = (irq < 32 ? 0 : 2);
- LIST_INSERT_HEAD(&au1000_cpuintrs[cpu_int].cintr_list, ih, ih_q);
+ LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q);
/*
* Now enable it.
*/
- if (au1000_intrtab[irq].intr_refcnt++ == 0) {
- icu_base = (irq < 32) ? IC0_BASE : IC1_BASE;
+ if (au_icu_intrtab[irq].intr_refcnt++ == 0) {
+ icu_base = (irq < 32) ? ic0_base : ic1_base;
irq &= 31; /* throw away high bit if set */
irq = 1 << irq; /* only used as a mask from here on */
- /* XXX Only high-level interrupts for now */
+ /* XXX Only level interrupts for now */
switch (type) {
case IST_NONE:
case IST_PULSE:
@@ -325,8 +267,8 @@
* Now, disable it, if there is nothing remaining on the
* list.
*/
- if (au1000_intrtab[irq].intr_refcnt-- == 1) {
- icu_base = (irq < 32) ? IC0_BASE : IC1_BASE;
+ if (au_icu_intrtab[irq].intr_refcnt-- == 1) {
+ icu_base = (irq < 32) ? ic0_base : ic1_base;
irq &= 31; /* throw away high bit if set */
irq = 1 << irq; /* only used as a mask from here on */
@@ -369,27 +311,27 @@
*/
switch (level) {
case 0:
- icu_base = IC0_BASE;
+ icu_base = ic0_base;
irqmask = REGVAL(icu_base + IC_REQUEST0_INT);
break;
case 1:
- icu_base = IC0_BASE;
+ icu_base = ic0_base;
irqmask = REGVAL(icu_base + IC_REQUEST1_INT);
break;
case 2:
- icu_base = IC1_BASE;
+ icu_base = ic1_base;
irqmask = REGVAL(icu_base + IC_REQUEST0_INT);
break;
case 3:
- icu_base = IC1_BASE;
+ icu_base = ic1_base;
irqmask = REGVAL(icu_base + IC_REQUEST1_INT);
break;
}
- au1000_cpuintrs[level].cintr_count.ev_count++;
- LIST_FOREACH(ih, &au1000_cpuintrs[level].cintr_list, ih_q) {
+ au_cpuintrs[level].cintr_count.ev_count++;
+ LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) {
/* XXX should check is see if interrupt is masked? */
if (1 << ih->ih_irq & irqmask) {
- au1000_intrtab[ih->ih_irq].intr_count.ev_count++;
+ au_icu_intrtab[ih->ih_irq].intr_count.ev_count++;
(*ih->ih_func)(ih->ih_arg);
REGVAL(icu_base + IC_MASK_CLEAR) = 1 << ih->ih_irq;
Index: sys/arch/mips/alchemy/aubus.c
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/alchemy/aubus.c,v
retrieving revision 1.1.1.1.6.1
diff -u -r1.1.1.1.6.1 aubus.c
--- sys/arch/mips/alchemy/aubus.c 10 Nov 2005 08:39:47 -0000 1.1.1.1.6.1
+++ sys/arch/mips/alchemy/aubus.c 11 Nov 2005 00:54:42 -0000
@@ -80,102 +80,9 @@
#include <machine/bus.h>
#include <machine/locore.h>
#include <mips/alchemy/include/aureg.h>
+#include <mips/alchemy/include/auvar.h>
#include <mips/alchemy/include/aubusvar.h>
-
-struct au1x00_dev {
- const char *name;
- bus_addr_t addr[3];
- int irq[2];
-};
-
-/*
- * The devices built in to the Au1000 CPU.
- */
-const struct au1x00_dev au1000_devs [] = {
- { "aucom", { UART0_BASE }, { 0, -1 }},
- { "aucom", { UART1_BASE }, { 1, -1 }},
- { "aucom", { UART2_BASE }, { 2, -1 }},
- { "aucom", { UART3_BASE }, { 3, -1 }},
- { "aurtc", { }, { -1, -1 }},
- { "aumac", { MAC0_BASE, MAC0_ENABLE, MAC0_DMA_BASE }, { 28, -1 }},
- { "aumac", { MAC1_BASE, MAC1_ENABLE, MAC1_DMA_BASE }, { 29, -1 }},
- { "auaudio", { AC97_BASE }, { 27, 31 }},
- { "ohci", { USBH_BASE, USBH_ENABLE, USBH_SIZE }, { 26, -1 }},
- { "usbd", { USBD_BASE }, { 24, 25 }},
- { "irda", { IRDA_BASE }, { 22, 23 }},
- { "gpio", { SYS_BASE }, { -1, -1 }},
- { "i2s", { I2S_BASE }, { -1, -1 }},
- { "ssi", { SSI0_BASE }, { 4, -1 }},
- { "ssi", { SSI1_BASE }, { 5, -1 }},
- { NULL }
-};
-
-/*
- * The devices built in to the Au1500 CPU.
- */
-const struct au1x00_dev au1500_devs [] = {
- { "aucom", { UART0_BASE }, { 0, -1 }},
- { "aucom", { UART3_BASE }, { 3, -1 }},
- { "aurtc", { }, { -1, -1 }},
- { "aumac", { AU1500_MAC0_BASE, AU1500_MAC0_ENABLE,
- MAC0_DMA_BASE }, { 28, -1 }},
- { "aumac", { AU1500_MAC1_BASE, AU1500_MAC1_ENABLE,
- MAC1_DMA_BASE }, { 29, -1 }},
- { "auaudio", { AC97_BASE }, { 27, 31 }},
- { "ohci", { USBH_BASE, USBH_ENABLE, USBH_SIZE }, { 26, -1 }},
- { "usbd", { USBD_BASE }, { 24, 25 }},
- { "gpio", { SYS_BASE }, { -1, -1 }},
- { "gpio2", { GPIO2_BASE }, { -1, -1 }},
- { "aupci", { }, { -1, -1 }},
- { NULL }
-};
-
-
-/*
- * The devices built in to the Au1550 CPU.
- */
-const struct au1x00_dev au1550_devs [] = {
- { "aucom", { UART0_BASE }, { 0, -1 }},
- { "aucom", { UART1_BASE }, { 8, -1 }},
- { "aucom", { UART3_BASE }, { 9, -1 }},
- { "aurtc", { }, { -1, -1 }},
- { "aumac", { MAC0_BASE, MAC0_ENABLE, MAC0_DMA_BASE }, { 27, -1 }},
- { "aumac", { MAC1_BASE, MAC1_ENABLE, MAC1_DMA_BASE }, { 28, -1 }},
- { "auaudio", { AC97_BASE }, { 27, 31 }},
- { "ohci", { AU1550_USBH_BASE, AU1550_USBH_ENABLE,
- AU1550_USBH_SIZE }, { 26, -1 }},
- { "usbd", { USBD_BASE }, { 24, 25 }},
- { "gpio", { SYS_BASE }, { -1, -1 }},
- { "gpio2", { GPIO2_BASE }, { -1, -1 }},
- { "aupci", { }, { -1, -1 }},
- { NULL }
-};
-
-/*
- * The devices built in to the Au1100 CPU.
- */
-const struct au1x00_dev au1100_devs [] = {
- { "aucom", { UART0_BASE }, { 0, -1 }},
- { "aucom", { UART1_BASE }, { 1, -1 }},
- { "aucom", { UART3_BASE }, { 3, -1 }},
- { "aurtc", { }, { -1, -1 }},
- { "aumac", { MAC0_BASE, MAC0_ENABLE, MAC0_DMA_BASE }, { 28, -1 }},
- { "auaudio", { AC97_BASE }, { 27, 31 }},
- { "ohci", { USBH_BASE, USBH_ENABLE, USBH_SIZE }, { 26, -1 }},
- { "usbd", { USBD_BASE }, { 24, 25 }},
- { "irda", { IRDA_BASE }, { 22, 23 }},
- { "gpio", { SYS_BASE }, { -1, -1 }},
- { "gpio2", { GPIO2_BASE }, { 29, -1 }},
- { "i2s", { I2S_BASE }, { 30, -1 }},
- { "ssi", { SSI0_BASE }, { 4, -1 }},
- { "ssi", { SSI1_BASE }, { 5, -1 }},
- { "sd0", { SD0_BASE }, { 5, -1 }},
- { "sd1", { SD1_BASE }, { 5, -1 }},
- { NULL }
-};
-
-
static int aubus_match(struct device *, struct cfdata *, void *);
static void aubus_attach(struct device *, struct device *, void *);
static int aubus_print(void *, const char *);
@@ -205,41 +112,27 @@
{
struct aubus_attach_args aa;
struct device *sc = (struct device *)self;
- const struct au1x00_dev *ad;
+ au_chipdep_t *chip;
int locs[AUBUSCF_NLOCS];
+ int i;
printf("\n");
- switch (MIPS_PRID_COPTS(cpu_id)) {
- case MIPS_AU1000:
- ad = au1000_devs;
- break;
- case MIPS_AU1500:
- ad = au1500_devs;
- break;
- case MIPS_AU1100:
- ad = au1100_devs;
- break;
- case MIPS_AU1550:
- ad = au1550_devs;
- break;
- default:
- panic("Unknown Alchemy SOC identification %d",
- MIPS_PRID_COPTS(cpu_id));
- }
+ chip = au_chipdep();
+ KASSERT(chip != NULL);
- for (; ad->name != NULL; ad++) {
- aa.aa_name = ad->name;
+ for (i = 0; chip->devices[i].name != NULL; i++) {
+ aa.aa_name = chip->devices[i].name;
aa.aa_st = aubus_st;
aa.aa_dt = &aubus_mdt;
aubus_alloc_dma_tag(sc, aa.aa_dt);
- aa.aa_addrs[0] = ad->addr[0];
- aa.aa_addrs[1] = ad->addr[1];
- aa.aa_addrs[2] = ad->addr[2];
- aa.aa_irq[0] = ad->irq[0];
- aa.aa_irq[1] = ad->irq[1];
+ aa.aa_addrs[0] = chip->devices[i].addr[0];
+ aa.aa_addrs[1] = chip->devices[i].addr[1];
+ aa.aa_addrs[2] = chip->devices[i].addr[2];
+ aa.aa_irq[0] = chip->devices[i].irq[0];
+ aa.aa_irq[1] = chip->devices[i].irq[1];
- locs[AUBUSCF_ADDR] = ad->addr[0];
+ locs[AUBUSCF_ADDR] = chip->devices[i].addr[0];
(void) config_found_sm_loc(self, "aubus", locs, &aa,
aubus_print, config_stdsubmatch);
Index: sys/arch/mips/alchemy/include/auvar.h
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/alchemy/include/auvar.h,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 auvar.h
--- sys/arch/mips/alchemy/include/auvar.h 9 Nov 2005 14:17:20 -0000 1.1.1.1
+++ sys/arch/mips/alchemy/include/auvar.h 11 Nov 2005 00:54:43 -0000
@@ -38,6 +38,36 @@
#ifndef _MIPS_ALCHEMY_AUVAR_H_
#define _MIPS_ALCHEMY_AUVAR_H_
+#include "opt_alchemy.h"
+
+typedef struct au_dev {
+ const char *name;
+ bus_addr_t addr[3];
+ int irq[2];
+} au_dev_t;
+
+typedef struct {
+ const char *name;
+ bus_addr_t icus[2]; /* in case it ever changes */
+ au_dev_t *devices;
+ const char **irqnames;
+} au_chipdep_t;
+
+au_chipdep_t *au_chipdep(void);
+
+#ifdef ALCHEMY_AU1000
+boolean_t au1000_match(au_chipdep_t **);
+#endif
+#ifdef ALCHEMY_AU1100
+boolean_t au1100_match(au_chipdep_t **);
+#endif
+#ifdef ALCHEMY_AU1500
+boolean_t au1500_match(au_chipdep_t **);
+#endif
+#ifdef ALCHEMY_AU1550
+boolean_t au1550_match(au_chipdep_t **);
+#endif
+
void au_intr_init(void);
void *au_intr_establish(int, int, int, int, int (*)(void *), void *);
void au_intr_disestablish(void *);
@@ -46,4 +76,5 @@
void au_cpureg_bus_mem_init(bus_space_tag_t, void *);
void au_cal_timers(bus_space_tag_t, bus_space_handle_t);
+
#endif /* _MIPS_ALCHEMY_AUVAR_H_ */
Index: sys/arch/mips/conf/files.alchemy
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/conf/files.alchemy,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 files.alchemy
--- sys/arch/mips/conf/files.alchemy 9 Nov 2005 14:17:20 -0000 1.1.1.1
+++ sys/arch/mips/conf/files.alchemy 11 Nov 2005 00:54:43 -0000
@@ -1,5 +1,15 @@
# $NetBSD: files.alchemy,v 1.3 2003/11/08 05:05:15 simonb Exp $
+defflag opt_alchemy.h ALCHEMY_AU1000
+ ALCHEMY_AU1100
+ ALCHEMY_AU1500
+ ALCHEMY_AU1550
+
+file arch/mips/alchemy/au_chipdep.c
+file arch/mips/alchemy/au1000_chipdep.c alchemy_au1000
+file arch/mips/alchemy/au1100_chipdep.c alchemy_au1100
+file arch/mips/alchemy/au1500_chipdep.c alchemy_au1500
+file arch/mips/alchemy/au1550_chipdep.c alchemy_au1550
file arch/mips/alchemy/au_icu.c
file arch/mips/alchemy/au_timer.c
file arch/mips/alchemy/au_cpureg_mem.c
--------------000102000305020503020705--