Subject: Re: port-evbmips/32030: Add support for Au1550 processor
To: None <port-evbmips-maintainer@netbsd.org, gnats-admin@netbsd.org,>
From: Garrett D'Amore <garrett_damore@tadpole.com>
List: netbsd-bugs
Date: 11/10/2005 08:39:02
The following reply was made to PR port-evbmips/32030; it has been noted by GNATS.

From: "Garrett D'Amore" <garrett_damore@tadpole.com>
To: gnats-bugs@netbsd.org
Cc: Simon Burge <simonb@wasabisystems.com>
Subject: Re: port-evbmips/32030: Add support for Au1550 processor
Date: Thu, 10 Nov 2005 00:38:11 -0800

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 Attached you will find the diffs for the support needed for the Au1550.
 
 A few notes:
 
 1) this includes changes that get USB to not crash, but the resulting 
 USB driver still does not work properly -- when you plug in a device you 
 get errors.  But it doesn't panic the kernel.  I am hoping to get some 
 help from AMD in understanding how else the USB driver differs from Au1500.
 
 2) the USB related changes should be merged against 31912 as well.
 
 3) obviously, this does not include PCI or other included peripheral 
 support -- just the support required for the Au1550 com and ethernet ports.
 
 4) note that this is tested on a DBAu1550 board -- which has different 
 PHYs (hence the addition of acphy)
 
 5) I'm not supporting a "revision 1" Au1 core on the Au1550 -- all 
 Alchemy parts after the Au1000 are revision 2 cores, anyway.
 
 Please let me know if you have any questions.  Thanks.
 
     -- Garrett
 
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 ? sys/arch/evbmips/compile/obj
 Index: sys/arch/mips/alchemy/aubus.c
 ===================================================================
 RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/alchemy/aubus.c,v
 retrieving revision 1.1.1.1
 diff -u -r1.1.1.1 aubus.c
 --- sys/arch/mips/alchemy/aubus.c	9 Nov 2005 14:17:20 -0000	1.1.1.1
 +++ sys/arch/mips/alchemy/aubus.c	10 Nov 2005 08:30:59 -0000
 @@ -101,7 +101,7 @@
  	{ "aumac",	{ MAC0_BASE, MAC0_ENABLE, MAC0_DMA_BASE }, { 28, -1 }},
  	{ "aumac",	{ MAC1_BASE, MAC1_ENABLE, MAC1_DMA_BASE }, { 29, -1 }},
  	{ "auaudio",	{ AC97_BASE },				   { 27, 31 }},
 -	{ "ohci",	{ USBH_BASE },				   { 26, -1 }},
 +	{ "ohci",	{ USBH_BASE, USBH_ENABLE, USBH_SIZE },	   { 26, -1 }},
  	{ "usbd",	{ USBD_BASE },				   { 24, 25 }},
  	{ "irda",	{ IRDA_BASE },				   { 22, 23 }},
  	{ "gpio",	{ SYS_BASE },				   { -1, -1 }},
 @@ -123,7 +123,7 @@
  	{ "aumac",	{ AU1500_MAC1_BASE, AU1500_MAC1_ENABLE,
  			      MAC1_DMA_BASE },			   { 29, -1 }},
  	{ "auaudio",	{ AC97_BASE },				   { 27, 31 }},
 -	{ "ohci",	{ USBH_BASE },				   { 26, -1 }},
 +	{ "ohci",	{ USBH_BASE, USBH_ENABLE, USBH_SIZE },	   { 26, -1 }},
  	{ "usbd",	{ USBD_BASE },				   { 24, 25 }},
  	{ "gpio",	{ SYS_BASE },				   { -1, -1 }},
  	{ "gpio2",	{ GPIO2_BASE },				   { -1, -1 }},
 @@ -133,6 +133,26 @@
  
  
  /*
 + * The devices built in to the Au1550 CPU.
 + */
 +const struct au1x00_dev au1550_devs [] = {
 +	{ "aucom",	{ UART0_BASE },				   {  0, -1 }},
 +	{ "aucom",	{ UART1_BASE },				   {  8, -1 }},
 +	{ "aucom",	{ UART3_BASE },				   {  9, -1 }},
 +	{ "aurtc",	{ },					   { -1, -1 }},
 +	{ "aumac",	{ MAC0_BASE, MAC0_ENABLE, MAC0_DMA_BASE }, { 27, -1 }},
 +	{ "aumac",	{ MAC1_BASE, MAC1_ENABLE, MAC1_DMA_BASE }, { 28, -1 }},
 +	{ "auaudio",	{ AC97_BASE },				   { 27, 31 }},
 +	{ "ohci",	{ AU1550_USBH_BASE, AU1550_USBH_ENABLE,
 +				AU1550_USBH_SIZE },		   { 26, -1 }},
 +	{ "usbd",	{ USBD_BASE },				   { 24, 25 }},
 +	{ "gpio",	{ SYS_BASE },				   { -1, -1 }},
 +	{ "gpio2",	{ GPIO2_BASE },				   { -1, -1 }},
 +	{ "aupci",	{ },					   { -1, -1 }},
 +	{ NULL }
 +};
 +
 +/*
   * The devices built in to the Au1100 CPU.
   */
  const struct au1x00_dev au1100_devs [] = {
 @@ -142,7 +162,7 @@
  	{ "aurtc",	{ },					   { -1, -1 }},
  	{ "aumac",	{ MAC0_BASE, MAC0_ENABLE, MAC0_DMA_BASE }, { 28, -1 }},
  	{ "auaudio",	{ AC97_BASE },				   { 27, 31 }},
 -	{ "ohci",	{ USBH_BASE },				   { 26, -1 }},
 +	{ "ohci",	{ USBH_BASE, USBH_ENABLE, USBH_SIZE },	   { 26, -1 }},
  	{ "usbd",	{ USBD_BASE },				   { 24, 25 }},
  	{ "irda",	{ IRDA_BASE },				   { 22, 23 }},
  	{ "gpio",	{ SYS_BASE },				   { -1, -1 }},
 @@ -200,6 +220,9 @@
  	case MIPS_AU1100:
  		ad = au1100_devs;
  		break;
 +	case MIPS_AU1550:
 +		ad = au1550_devs;
 +		break;
  	default:
  		panic("Unknown Alchemy SOC identification %d",
  		    MIPS_PRID_COPTS(cpu_id));
 Index: sys/arch/mips/alchemy/dev/ohci_aubus.c
 ===================================================================
 RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/alchemy/dev/ohci_aubus.c,v
 retrieving revision 1.1.1.1
 diff -u -r1.1.1.1 ohci_aubus.c
 --- sys/arch/mips/alchemy/dev/ohci_aubus.c	9 Nov 2005 14:17:20 -0000	1.1.1.1
 +++ sys/arch/mips/alchemy/dev/ohci_aubus.c	10 Nov 2005 08:30:59 -0000
 @@ -85,15 +85,18 @@
  	void *ih;
  	usbd_status r;
  	uint32_t x, tmp;
 +	bus_addr_t usbh_base, usbh_enable;
  	struct aubus_attach_args *aa = aux;
  
  	r = 0;
  
 -	sc->sc_size = USBH_SIZE;
 +	usbh_base = aa->aa_addrs[0];
 +	usbh_enable = aa->aa_addrs[1];
 +	sc->sc_size = aa->aa_addrs[2];
  	sc->iot = aa->aa_st;
  	sc->sc_bus.dmatag = (bus_dma_tag_t)aa->aa_dt;
  
 -	if (bus_space_map(sc->iot, USBH_BASE, USBH_SIZE, 0, &sc->ioh)) {
 +	if (bus_space_map(sc->iot, usbh_base, sc->sc_size, 0, &sc->ioh)) {
  		printf("%s: Unable to map USBH registers\n",
  			sc->sc_bus.bdev.dv_xname);
  		return;
 @@ -107,15 +110,15 @@
  	 *  (3) Clear HCFS in OHCI_CONTROL.
  	 *  (4) Wait for RD bit to be set.
  	 */
 -	x = bus_space_read_4(sc->iot, sc->ioh, USBH_ENABLE);
 +	x = bus_space_read_4(sc->iot, sc->ioh, usbh_enable);
  	x |= UE_CE;
 -	bus_space_write_4(sc->iot, sc->ioh, USBH_ENABLE, x);
 +	bus_space_write_4(sc->iot, sc->ioh, usbh_enable, x);
  	delay(10);
  	x |= UE_E;
  #ifdef __MIPSEB__
  	x |= UE_BE;
  #endif
 -	bus_space_write_4(sc->iot, sc->ioh, USBH_ENABLE, x);
 +	bus_space_write_4(sc->iot, sc->ioh, usbh_enable, x);
  	delay(10);
  	x = bus_space_read_4(sc->iot, sc->ioh, OHCI_CONTROL);
  	x &= ~(OHCI_HCFS_MASK);
 @@ -125,13 +128,13 @@
           *  au1500 Errata #7.
           */
  	for (x = 100; x; x--) {
 -		bus_space_read_4(sc->iot, sc->ioh, USBH_ENABLE);
 -		tmp = bus_space_read_4(sc->iot, sc->ioh, USBH_ENABLE);
 +		bus_space_read_4(sc->iot, sc->ioh, usbh_enable);
 +		tmp = bus_space_read_4(sc->iot, sc->ioh, usbh_enable);
  		if (tmp&UE_RD)
  			break;
  		delay(1000);
  	}
 -	printf(": Au1X00 OHCI\n");
 +	printf(": Alchemy OHCI\n");
  
  	/* Disable OHCI interrupts */
  	bus_space_write_4(sc->iot, sc->ioh, OHCI_INTERRUPT_DISABLE,
 Index: sys/arch/mips/alchemy/include/aureg.h
 ===================================================================
 RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/alchemy/include/aureg.h,v
 retrieving revision 1.1.1.1
 diff -u -r1.1.1.1 aureg.h
 --- sys/arch/mips/alchemy/include/aureg.h	9 Nov 2005 14:17:20 -0000	1.1.1.1
 +++ sys/arch/mips/alchemy/include/aureg.h	10 Nov 2005 08:31:00 -0000
 @@ -177,7 +177,11 @@
  #define	  UE_C			  0x00000002	/* coherent */
  #define	  UE_BE			  0x00000001	/* big-endian */
  
 -#define	USBH_SIZE		0x80000		/* size of register set */
 +#define	USBH_SIZE		0x100000	/* size of register set */
 +
 +#define	AU1550_USBH_BASE	0x14020000
 +#define	AU1550_USBH_ENABLE	0x7ffc
 +#define AU1550_USBH_SIZE	0x60000
  
  /************************************************************************/
  /**********************   USB Device registers   ************************/
 Index: sys/arch/mips/include/cpuregs.h
 ===================================================================
 RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/include/cpuregs.h,v
 retrieving revision 1.1.1.1
 diff -u -r1.1.1.1 cpuregs.h
 --- sys/arch/mips/include/cpuregs.h	9 Nov 2005 14:17:20 -0000	1.1.1.1
 +++ sys/arch/mips/include/cpuregs.h	10 Nov 2005 08:31:00 -0000
 @@ -778,6 +778,7 @@
  #define	MIPS_AU1000	0x00
  #define	MIPS_AU1500	0x01
  #define	MIPS_AU1100	0x02
 +#define	MIPS_AU1550	0x03
  
  /*
   * CPU processor revision IDs for company ID == 4 (SiByte)
 Index: sys/arch/mips/mips/mips_machdep.c
 ===================================================================
 RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/mips/mips_machdep.c,v
 retrieving revision 1.1.1.1
 diff -u -r1.1.1.1 mips_machdep.c
 --- sys/arch/mips/mips/mips_machdep.c	9 Nov 2005 14:17:20 -0000	1.1.1.1
 +++ sys/arch/mips/mips/mips_machdep.c	10 Nov 2005 08:31:03 -0000
 @@ -409,6 +409,10 @@
  	  MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
  						"Au1100 (Rev 2 core)" 	},
  
 +	{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1550, -1, 0,
 +	  MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
 +						"Au1550 (Rev 2 core)" 	},
 +
  	/* The SB-1 CPU uses a CCA of 5 - "Cacheable Coherent Shareable" */
  	{ MIPS_PRID_CID_SIBYTE, MIPS_SB1, -1,	-1, -1, 0,
  	  MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT |
 Index: sys/arch/evbmips/conf/PB1000
 ===================================================================
 RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/evbmips/conf/PB1000,v
 retrieving revision 1.1.1.1
 diff -u -r1.1.1.1 PB1000
 --- sys/arch/evbmips/conf/PB1000	9 Nov 2005 14:17:15 -0000	1.1.1.1
 +++ sys/arch/evbmips/conf/PB1000	10 Nov 2005 08:31:03 -0000
 @@ -143,6 +143,7 @@
  amhphy*		at mii? phy ?			# AMD 79c901 Ethernet PHYs
  bmtphy*		at mii? phy ?			# Broadcom BCM5201/BCM5202 PHYs
  sqphy*		at mii? phy ?			# Seeq 80220/80221/80223 PHYs
 +acphy*		at mii? phy ?			# AMD/Altima AC101 PHYs
  
  # USB
  ohci*		at aubus? addr ?		# USB Open Host Controller
 
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