On Wed, Mar 13, 2002 at 10:36:31PM +0100, Manuel Bouyer wrote:
> On Tue, Mar 12, 2002 at 11:41:00PM +0000, David Laight wrote:
> > I think it is possible to detect a value it the status register
> > that can only have happened if the command has completed.
> > (This may require sending an illegal commands to get an error
> > status set first).
> 
> Well, we're talking about a test needed for all interrupts here

Not really, you just need to write the device driver such that
its ISR can be entered at any time, and it decides what to do
given the contents of the STATUS register and the last command
issued.

I've just been reading T13/1153D revsion 18 (again)....

I would ensure that the ISR:
1) always reads STATUS to ensure the hardware IRQ is removed
2) if BUSY set, return
3) if DRQ set request data xfer (unless dma active) and return
4) if no command active, return
5) if ERR set, report error and/or retry
6) if < 400ns since command issued, wait on short timer
7) report command complete

IRQ is 'taken' if you return at 3, 5 or 7.

For most systems the system interrupt entry sequence is
probably longer than 400ns!  (you only need to wait 400ns
to ensure the contents of STATUS is valid, reading it
earlier isn't a problem).

The 400ns is probably only relevant when issuing write or
packet commands - where there is no interrupt before the
first data transfer, and you are polling for DRQ.

Might be a problem doing commands with no data in a poll
mode driver.  But these aren't usually performance critical.

	David

-- 
David Laight: david@l8s.co.uk