On Sunday 04 February 2001  5:13 pm, Manuel Bouyer wrote:
> On Sun, Feb 04, 2001 at 04:25:25PM +0000, Chris Gilbert wrote:
> > Looking at sys/macppc/dev/wdc_obio.c it doesn't have this flag set, and
> > it uses wdc_print_modes (AFAIR it's the original reason for having
> > wdc_print_modes)  Is it also wrong?  or have I missed something? (which
> > is probably more likely)
>
> This front-end looks quite brocken, especially the adjust_timing() stuff.
> It shoud use the set_modes callback instead, and assert
> WDC_CAPABILITY_MODE. I'll look at this later (but I can't test it).
>
> Note that it never updates PIO_mode and DMA_mode, so the infos printed
> here are surely not accurate. I think it's there only to inform that
> DMA is used.

Ahh, no point copying broken code then.  Certainly the reason for me adding 
is was to just get more info.  I just prefer that people are aware that 
controllers aren't using DMA even if the drives are.  The adding the 
wdc_print_modes makes the output on my arm32 box:

rapide0 at podulebus0 [ podule 1 ]: Issue 2
atapibus0 at rapide0 channel 0
cd0 at atapibus0 drive 1: <CD-540E, , 1.0A> type 5 cdrom removable

cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 2 (Ultra/33)
wd0 at rapide0 channel 0 drive 0: <QUANTUM FIREBALL SE4.3A>
wd0: drive supports 16-sector PIO transfers, LBA addressing
wd0: 4110 MB, 14848 cyl, 9 head, 63 sec, 512 bytes/sect x 8418816 sectors
 
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 2 (Ultra/33)
wd0(rapide0:0:0): using PIO mode 4
cd0(rapide0:0:1): using PIO mode 4
wd1 at rapide0 channel 1 drive 0: <QUANTUM FIREBALL1280A>
wd1: drive supports 8-sector PIO transfers, LBA addressing
wd1: 1222 MB, 2484 cyl, 16 head, 63 sec, 512 bytes/sect x 2503872 sectors
 
wd1: drive supports PIO mode 4, DMA mode 2
wd1(rapide0:1:0): using PIO mode 4

So I believe that this needs tackling from a different direction?

Cheers,
Chris