>Number:         11747
>Category:       kern
>Synopsis:       Can't UDMA5 (Ultra ATA/100) on Intel ICH2
>Confidential:   no
>Severity:       non-critical
>Priority:       medium
>Responsible:    kern-bug-people
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Fri Dec 15 03:15:01 PST 2000
>Closed-Date:
>Last-Modified:
>Originator:     Tomokazu HARADA
>Release:        NetBSD-current
>Organization:
	Department of Mathematics, Okayama University
>Environment:
System: NetBSD ems 1.5N NetBSD 1.5N (GENERIC) #2: Fri Dec 15 13:18:39 JST 2000     tmk@ems:/usr/c/src/sys/arch/i386/compile/GENERIC i386

>Description:
	Intel ICH2 supports UDMA mode 5 (Ultra ATA/100).  But, it is
	configured for UDMA mode 4 even if drive supports UDMA mode 5.

pciide0 at pci0 dev 31 function 1: Intel 82801BA IDE Controller (ICH2) (rev. 0x01)

wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
wd0(pciide0:0:0): using PIO mode 4, Ultra-DMA mode 4 (Ultra/66) (using DMA data transfers)

>How-To-Repeat:
	Boot a PC with an Intel i815E chipset + UDMA5 HDD.
>Fix:
	Apply the following patch.  The patch also enables debug prints
	on ICH2.

--- pciide.c	2000/12/04 20:25:40	1.96
+++ pciide.c	2000/12/14 18:50:11
@@ -1343,8 +1343,10 @@
 	sc->sc_wdcdev.PIO_cap = 4;
 	sc->sc_wdcdev.DMA_cap = 2;
 	switch(sc->sc_pp->ide_product) {
-	case PCI_PRODUCT_INTEL_82801AA_IDE:
 	case PCI_PRODUCT_INTEL_82801BA_IDE:
+		sc->sc_wdcdev.UDMA_cap = 5;
+		break;
+	case PCI_PRODUCT_INTEL_82801AA_IDE:
 		sc->sc_wdcdev.UDMA_cap = 4;
 		break;
 	default:
@@ -1370,7 +1372,8 @@
 			    DEBUG_PROBE);
 		}
 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
-		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) {
+		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
+		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE) {
 			WDCDEBUG_PRINT((", IDE_CONTROL 0x%x",
 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
 			    DEBUG_PROBE);
@@ -1420,7 +1423,8 @@
 			    DEBUG_PROBE);
 		}
 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
-		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) {
+		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
+		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE) {
 			WDCDEBUG_PRINT((", IDE_CONTROL 0x%x",
 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
 			    DEBUG_PROBE);
@@ -1579,8 +1583,27 @@
 			goto pio;
 
 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
-		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) {
+		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
+		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE) {
 			ideconf |= PIIX_CONFIG_PINGPONG;
+		}
+		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE) {
+			/* setup Ultra/100 */
+			if (drvp->UDMA_mode > 2 &&
+			    (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
+				drvp->UDMA_mode = 2;
+			if (drvp->UDMA_mode > 4) {
+				ideconf |= PIIX_CONFIG_UDMA100(channel, drive);
+			} else {
+				ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive);
+				if (drvp->UDMA_mode > 2) {
+					ideconf |= PIIX_CONFIG_UDMA66(channel,
+					    drive);
+				} else {
+					ideconf &= ~PIIX_CONFIG_UDMA66(channel,
+					    drive);
+				}
+			}
 		}
 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) {
 			/* setup Ultra/66 */
--- pciide_piix_reg.h	2000/05/15 08:46:01	1.4
+++ pciide_piix_reg.h	2000/12/14 18:52:55
@@ -99,13 +99,15 @@
 	(((x) << ((channel * 8) + (drive * 4))) << PIIX_UDMATIM_SHIFT)
 
 /*
- * IDE config register (ICH/ICH0 only)
+ * IDE config register (ICH/ICH0/ICH2 only)
  */
 #define PIIX_CONFIG	0x54
 #define PIIX_CONFIG_PINGPONG	0x0400
-/* The following are only for the 82801AA (ICH) */
+/* The following are only for 82801AA (ICH) and 82801BA (ICH2) */
 #define PIIX_CONFIG_CR(channel, drive) (0x0010 << ((channel) * 2 + (drive)))
 #define PIIX_CONFIG_UDMA66(channel, drive) (0x0001 << ((channel) * 2 + (drive)))
+/* The following are only for the 82801BA (ICH2) */
+#define PIIX_CONFIG_UDMA100(channel, drive) (0x1000 << ((channel) * 2 + (drive)))
 
 /*
  * these tables define the differents values to upload to the
@@ -116,4 +118,4 @@
 static int8_t piix_rtc_pio[] = {0x00, 0x00, 0x00, 0x01, 0x03};
 static int8_t piix_isp_dma[] = {0x00, 0x02, 0x02};
 static int8_t piix_rtc_dma[] = {0x00, 0x02, 0x03};
-static int8_t piix4_sct_udma[] = {0x00, 0x01, 0x02, 0x01, 0x02};
+static int8_t piix4_sct_udma[] = {0x00, 0x01, 0x02, 0x01, 0x02, 0x01};
>Release-Note:
>Audit-Trail:
>Unformatted: