>Number:         9907
>Category:       port-mips
>Synopsis:       upte's PG_G bit does not take effect on mips3_switch_resume()
>Confidential:   no
>Severity:       serious
>Priority:       high
>Responsible:    port-mips-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Sun Apr 16 21:43:00 PDT 2000
>Closed-Date:
>Last-Modified:
>Originator:     Shuichiro URATA
>Release:        NetBSD/arc current
>Organization:
>Environment:

>Description:
In mips3_switch_resume(), write operation of TLB entry #1 sets PG_G bit
on lo0, but 0 on lo1. Actual PG_G bit on TLB entry is shared between
lo0 and lo1, and it's written logical AND value of lo0 and lo1.
So PG_G bit on lo0 doesn't take effect.

>How-To-Repeat:

>Fix:
Apply this patch.

*** locore_mips3.S.orig	Sun Apr 16 20:09:41 2000
--- locore_mips3.S	Sun Apr 16 20:50:18 2000
***************
*** 2251,2257 ****
  	mtc0	s0, MIPS_COP_0_TLB_INDEX	# TLB entry #1
  	or	a2, MIPS3_PG_G
  	dmtc0	a2, MIPS_COP_0_TLB_LO0		# lo0: upte[1] | PG_G
! 	dmtc0	zero, MIPS_COP_0_TLB_LO1	# lo1: none
  	nop
  	nop
  	tlbwi					# set TLB entry #1
--- 2251,2258 ----
  	mtc0	s0, MIPS_COP_0_TLB_INDEX	# TLB entry #1
  	or	a2, MIPS3_PG_G
  	dmtc0	a2, MIPS_COP_0_TLB_LO0		# lo0: upte[1] | PG_G
! 	li	a2, MIPS3_PG_G
! 	dmtc0	a2, MIPS_COP_0_TLB_LO1		# lo1: none
  	nop
  	nop
  	tlbwi					# set TLB entry #1

>Release-Note:
>Audit-Trail:
>Unformatted: