AMD provides a glimpse of Hammer MPU


By Jerry Ascierto
EE Times
(10/16/01, 3:47 p.m. EST)

SAN JOSE, Calif. AMD hopes the architecture will expand its presence in the 4-way and 8-way enterprise market, while serving as a platform personal computing markets. AMD's approach to 64-bit computing looks to make the migration away from 32-bit as painless as possible, with the Hammer running both 32-bit and 64-bit software.

"This is more than just a new microprocessor," said Fred Weber, vice president and chief technical officer of the Computation Products Group of AMD (Sunnyvale, Calif.). "We're building a next-generation system architecture which will serve as foundation for multiple generations of future processors. It will provide a top-to-bottom road map for desktop and mobile processors in addition to servers and workstations."

Among the key features Weber tipped in his presentation were the architecture's pervasive use of the HyperTransport interconnect, a scalable system bus with support for single-processor and multiprocessor configurations, and an integrated DDR memory controller.

The 64-bit migration path AMD has laid down for Hammer was designed to preserve investments in X86 software. "The vast majority of our customers would like to stay in the existing instruction set," Weber said. "The instruction set should be thought of as a vehicle of compatibility, not performance."

Similarly with 32-bit computing, AMD's approach leaves the vast majority of the instruction set's op codes and features unchanged, while new enhancements look to be transparent. Eight new integer registers, PC relative addressing, and full support for SSE/SSEII-based floating-point application binary interface (ABI) were added to the set, which seeks to offer the code density of CISC architectures along with the register usage and ABI models of RISC, AMD said.

The integrated DDR memory controller supports 8-byte and 16-byte interfaces, and the 16-byte interface supports a direct connection to 8 registered dual-in-line memory modules and to Chipkill error-correction code (ECC). "The controller scales memory latency, so as the CPU and HyperTransport link speeds improve, memory latency does as well," Weber said. "The bandwidth to memory increases every time you add a CPU."

Built-in reliability features include L1 data cache, L2 cache, cache tags and DRAM, all ECC protected. The cache subsystem comes with enhanced TLB structures and improved branch prediction.

"We improved the frequency over previous generations by judiciously adding more pipeline stages," Weber said. "With Hammer there's tremendous support for large workloads," with the enhanced TLB [table lookaside buffer] structures, highly associative caches and branch prediction, as well as with a scalable memory and I/O subsystem, he said.

The architecture's combination of features adds up to a Spec (Standard Performance Evaluation Corp.) benchmark rating that's "two times the best spec scores people are reporting today," Weber said.

Analysts believe the chip will be a formidable foe for Intel's Itanium. "When Intel sees this chip, if they weren't worried about this before, they should be," said Nathan Brookwood, president of market-research firm Insight64. The difficulty will be in marketing, market perception and proliferation, he said. "The problem that AMD may have is, who will they be selling this to?"

http://www.eet.com/story/OEG20011016S0092