Re: powerpc/pic/intr.c IPL_HIGH vs IPL_NONE

[Frank Wille <frank%phoenix.owl.de@localhost>]

On Thu, 3 Jan 2013 20:59:16 -0800
Matt Thomas <matt%3am-software.com@localhost> wrote:

> Actually I think the pic should be entered with IPL_HIGH and let the
> lower priority interrupts (if any) be serviced by the pending int
> mechanism.

Ok. That would be acceptable.

So the interrupt for a cascaded PIC should always be established with
IPL_HIGH instead of IPL_NONE?

We would have to change that in a few locations:

bebox/bebox/machdep.c:  intr_establish(16 + 26, IST_LEVEL, IPL_NONE, 
pic_handle_intr, isa_pic);
evbppc/ev64260/gt_mainbus.c:    intr_establish(IRQ_GPP7_0, IST_LEVEL, IPL_NONE,
evbppc/ev64260/gt_mainbus.c:    intr_establish(IRQ_GPP15_8, IST_LEVEL, IPL_NONE,
evbppc/ev64260/gt_mainbus.c:    intr_establish(IRQ_GPP23_16, IST_LEVEL, 
IPL_NONE,
evbppc/ev64260/gt_mainbus.c:    intr_establish(IRQ_GPP31_24, IST_LEVEL, 
IPL_NONE,
macppc/macppc/pic_ohare.c:      intr_establish(irq, IST_LEVEL, IPL_NONE, 
pic_handle_intr, pic);
ofppc/ofppc/mainbus.c:          intr_establish(16, IST_LEVEL, IPL_NONE, 
pic_handle_intr,
powerpc/ibm4xx/pic_uic.c:       intr_establish(30, IST_LEVEL, IPL_NONE, 
pic_handle_intr, &pic_uic1);
powerpc/ibm4xx/pic_uic.c:       intr_establish(28, IST_LEVEL, IPL_NONE, 
pic_handle_intr, &pic_uic2);
prep/prep/machdep.c:            intr_establish(16, IST_LEVEL, IPL_NONE, 
pic_handle_intr,
sandpoint/sandpoint/machdep.c:  intr_establish(16, IST_LEVEL, IPL_NONE, 
pic_handle_intr, isa_pic);

@kiyohara: Did you already verify that it works for BeBox?


>  Note that any sources with an IPL_HIGH can be serviced
> directly.

I don't understand that. When calling pic_handle_intr() for the cascaded
PIC at IPL_HIGH, then pcpl is IPL_HIGH there.

Which means that
  if ((imask[pcpl] & v_imen) != 0)
would be true and an IPL_HIGH interrupt at the cascaded PIC is also
marked as pending.

It would probably be handled at splx() on the primary PIC later.

-- 
Frank Wille