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Re: Debugging ahcisata?
On Tue, 18 Aug 2009, KIYOHARA Takashi wrote:
Well, I tried adding this controller to the lists of valid devices for
mvsata, but at boot time it failed with "can't map any registers" so I
guess mvsata is probably not going to work!
hmm...
Can you give me your dmesg with 'options PCI_CONFIG_DUMP'?
The whole dmesg overflowed the buffer, but it _was_ able to capture the
important parts. Search for pci8 in the attached file...
-------------------------------------------------------------------------
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| Kernel Developer | | pgoyette at netbsd.org |
-------------------------------------------------------------------------
(UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: PCI (0x04)
Interface: 0x00
Revision ID: 0xa2
BIST: 0x00
Header Type: 0x01 (0x01)
Latency Timer: 0x00
Cache Line Size: 0x08
Type 1 (PCI-PCI bridge) header:
0x10: 0x00000000 0x00000000 0x00070700 0x000001f1
0x20: 0x0000fff0 0x0001fff1 0x00000000 0x00000000
0x30: 0x00000000 0x00000040 0x00000000 0x000400ff
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Primary bus number: 0x00
Secondary bus number: 0x07
Subordinate bus number: 0x07
Secondary bus latency timer: 0x00
Secondary status register: 0x0000
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Signaled Target Abort: off
Received Target Abort: off
Received Master Abort: off
System Error: off
Parity Error: off
I/O region:
base register: 0xf1
limit register: 0x01
base upper 16 bits register: 0x0000
limit upper 16 bits register: 0x0000
Memory region:
base register: 0xfff0
limit register: 0x0000
Prefetchable memory region:
base register: 0xfff1
limit register: 0x0001
base upper 32 bits register: 0x00000000
limit upper 32 bits register: 0x00000000
Capability list pointer: 0x40
Expansion ROM Base Address: 0x00000000
Interrupt line: 0xff
Interrupt pin: 0x00 (none)
Bridge control register: 0x0004
Parity error response: off
Secondary SERR forwarding: off
ISA enable: on
VGA enable: off
Master abort reporting: off
Secondary bus reset: off
Fast back-to-back capable: off
Capability register at 0x40
type: 0x0d (unknown)
Capability register at 0x48
type: 0x01 (Power Management, rev. 1.0)
Capability register at 0x50
type: 0x05 (MSI)
Capability register at 0x60
type: 0x08 (LDT)
Capability register at 0x80
type: 0x10 (PCI Express)
PCI Power Management Capabilities Register
Capabilities register: 0xf802
Version: 1.1
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support: 0x1f
Control/status register: 0x0000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion disabled
PME# status: off
PCI Express Capabilities Register
Capability version: 1
Device type: Root Port of PCI Express Root Complex
Slot implemented
Interrupt Message Number: 0
Slot Control Register:
Attention Indictor Control: blink
Power Indictor Control: on
Power Controller Control: on
Device-dependent header:
0x40: 0x0000480d 0x000010de 0xf8025001 0x00000000
0x50: 0x00826005 0x00000000 0x00000000 0x00000000
0x60: 0xa8008008 0xfee00000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x01410010 0x000084c1 0x00002830 0x02113c11
0x90: 0x10410000 0x00000000 0x000001c0 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
vendor 0x10de product 0x0378 (PCI bridge, revision 0xa2) at ? dev 21 function 0
(intrswiz 0, intrpin 0, i/o off, mem off, no quirks): vendor 0x10de product
0x0378 (rev. 0xa2)
pci7 at ppb6 bus 7
pci7: no spaces enabled!
ppb7 at pci0 dev 22 function 0: PCI configuration registers:
Common header:
0x00: 0x037510de 0x00100007 0x060400a2 0x00010008
Vendor ID: 0x10de
Device ID: 0x0375
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: PCI (0x04)
Interface: 0x00
Revision ID: 0xa2
BIST: 0x00
Header Type: 0x01 (0x01)
Latency Timer: 0x00
Cache Line Size: 0x08
Type 1 (PCI-PCI bridge) header:
0x10: 0x00000000 0x00000000 0x00080800 0x20008181
0x20: 0xfdc0fdc0 0x0001fff1 0x00000000 0x00000000
0x30: 0x00000000 0x00000040 0x00000000 0x000400ff
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Primary bus number: 0x00
Secondary bus number: 0x08
Subordinate bus number: 0x08
Secondary bus latency timer: 0x00
Secondary status register: 0x2000
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Signaled Target Abort: off
Received Target Abort: off
Received Master Abort: on
System Error: off
Parity Error: off
I/O region:
base register: 0x81
limit register: 0x81
base upper 16 bits register: 0x0000
limit upper 16 bits register: 0x0000
Memory region:
base register: 0xfdc0
limit register: 0xfdc0
Prefetchable memory region:
base register: 0xfff1
limit register: 0x0001
base upper 32 bits register: 0x00000000
limit upper 32 bits register: 0x00000000
Capability list pointer: 0x40
Expansion ROM Base Address: 0x00000000
Interrupt line: 0xff
Interrupt pin: 0x00 (none)
Bridge control register: 0x0004
Parity error response: off
Secondary SERR forwarding: off
ISA enable: on
VGA enable: off
Master abort reporting: off
Secondary bus reset: off
Fast back-to-back capable: off
Capability register at 0x40
type: 0x0d (unknown)
Capability register at 0x48
type: 0x01 (Power Management, rev. 1.0)
Capability register at 0x50
type: 0x05 (MSI)
Capability register at 0x60
type: 0x08 (LDT)
Capability register at 0x80
type: 0x10 (PCI Express)
PCI Power Management Capabilities Register
Capabilities register: 0xf802
Version: 1.1
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support: 0x1f
Control/status register: 0x0000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion disabled
PME# status: off
PCI Express Capabilities Register
Capability version: 1
Device type: Root Port of PCI Express Root Complex
Slot implemented
Interrupt Message Number: 0
Slot Control Register:
Attention Indictor Control: blink
Power Indictor Control: on
Power Controller Control: on
Device-dependent header:
0x40: 0x0000480d 0x000010de 0xf8025001 0x00000000
0x50: 0x00826005 0x00000000 0x00000000 0x00000000
0x60: 0xa8008008 0xfee00000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x01410010 0x000084c1 0x00002810 0x01113c11
0x90: 0x30110040 0x00000000 0x014801c0 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
vendor 0x10de product 0x0375 (PCI bridge, revision 0xa2) at ? dev 22 function 0
(intrswiz 0, intrpin 0, i/o on, mem on, no quirks): vendor 0x10de product
0x0375 (rev. 0xa2)
pci8 at ppb7 bus 8
pci8: i/o space, memory space enabled, rd/line, wr/inv ok
mvsata0 at pci8 dev 0 function 0: PCI configuration registers:
Common header:
0x00: 0x614111ab 0x00100007 0x01068101 0x00000008
Vendor ID: 0x11ab
Device ID: 0x6141
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: mass storage (0x01)
Subclass Name: SATA (0x06)
Interface: 0x81
Revision ID: 0x01
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0x08
Type 0 ("normal" device) header:
0x10: 0x00008c01 0x00008801 0x00008401 0x00000000
0x20: 0x00008001 0xfdcff000 0x00000000 0x81d61043
0x30: 0xfdc80000 0x00000048 0x00000000 0x0008010b
Base address register at 0x10
type: 32-bit i/o
base: 0x00008c00, size: 0x00000008
Base address register at 0x14
type: 32-bit i/o
base: 0x00008800, size: 0x00000004
Base address register at 0x18
type: 32-bit i/o
base: 0x00008400, size: 0x00000040
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
type: 32-bit i/o
base: 0x00008000, size: 0x00000020
Base address register at 0x24
type: 32-bit nonprefetchable memory
base: 0xfdcff000, size: 0x00000400
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1043
Subsystem ID: 0x81d6
Expansion ROM Base Address: 0xfdc80000
Capability list pointer: 0x48
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x08
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0b
Capability register at 0x48
type: 0x01 (Power Management, rev. 1.0)
Capability register at 0x50
type: 0x05 (MSI)
Capability register at 0xe0
type: 0x10 (PCI Express)
PCI Power Management Capabilities Register
Capabilities register: 0x5a02
Version: 1.1
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: on
D2 power management state support: off
PME# support: 0x0b
Control/status register: 0x2000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion disabled
PME# status: off
PCI Express Capabilities Register
Capability version: 1
Device type: Legacy PCI Express Endpoint device
Interrupt Message Number: 0
Device-dependent header:
0x40: 0x00f0f6db 0x0010001f 0x5a025001 0x13002000
0x50: 0x0000e005 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x000000b0 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00110010 0x00200fc0 0x00080400 0x0103a411
0xf0: 0x10110040 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
vendor 0x11ab product 0x6141 (SATA mass storage, interface 0x81, revision 0x01)
at ? dev 0 function 0 (intrswiz 0, intrpin 0x1, i/o on, mem on, no quirks):
vendor 0x11ab product 0x6141
pci_mem_find: expected type mem, found i/o
mvsata0: can't map registers
ppb8 at pci0 dev 23 function 0: PCI configuration registers:
Common header:
0x00: 0x037710de 0x00100000 0x060400a2 0x00010008
Vendor ID: 0x10de
Device ID: 0x0377
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: PCI (0x04)
Interface: 0x00
Revision ID: 0xa2
BIST: 0x00
Header Type: 0x01 (0x01)
Latency Timer: 0x00
Cache Line Size: 0x08
Type 1 (PCI-PCI bridge) header:
0x10: 0x00000000 0x00000000 0x00090900 0x000001f1
0x20: 0x0000fff0 0x0001fff1 0x00000000 0x00000000
0x30: 0x00000000 0x00000040 0x00000000 0x000400ff
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Primary bus number: 0x00
Secondary bus number: 0x09
Subordinate bus number: 0x09
Secondary bus latency timer: 0x00
Secondary status register: 0x0000
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Signaled Target Abort: off
Received Target Abort: off
Received Master Abort: off
System Error: off
Parity Error: off
I/O region:
base register: 0xf1
limit register: 0x01
base upper 16 bits register: 0x0000
limit upper 16 bits register: 0x0000
Memory region:
base register: 0xfff0
limit register: 0x0000
Prefetchable memory region:
base register: 0xfff1
limit register: 0x0001
base upper 32 bits register: 0x00000000
limit upper 32 bits register: 0x00000000
Capability list pointer: 0x40
Expansion ROM Base Address: 0x00000000
Interrupt line: 0xff
Interrupt pin: 0x00 (none)
Bridge control register: 0x0004
Parity error response: off
Secondary SERR forwarding: off
ISA enable: on
VGA enable: off
Master abort reporting: off
Secondary bus reset: off
Fast back-to-back capable: off
Capability register at 0x40
type: 0x0d (unknown)
Capability register at 0x48
type: 0x01 (Power Management, rev. 1.0)
Capability register at 0x50
type: 0x05 (MSI)
Capability register at 0x60
type: 0x08 (LDT)
Capability register at 0x80
type: 0x10 (PCI Express)
PCI Power Management Capabilities Register
Capabilities register: 0xf802
Version: 1.1
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: off
D2 power management state support: off
PME# support: 0x1f
Control/status register: 0x0000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion disabled
PME# status: off
PCI Express Capabilities Register
Capability version: 1
Device type: Root Port of PCI Express Root Complex
Slot implemented
Interrupt Message Number: 0
Slot Control Register:
Attention Indictor Control: blink
Power Indictor Control: on
Power Controller Control: on
Device-dependent header:
0x40: 0x0000480d 0x000010de 0xf8025001 0x00000000
0x50: 0x00826005 0x00000000 0x00000000 0x00000000
0x60: 0xa8008008 0xfee00000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x01410010 0x000084c1 0x00002810 0x00113d01
0x90: 0x11010000 0x00000000 0x000001c0 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
vendor 0x10de product 0x0377 (PCI bridge, revision 0xa2) at ? dev 23 function 0
(intrswiz 0, intrpin 0, i/o off, mem off, no quirks): vendor 0x10de product
0x0377 (rev. 0xa2)
pci9 at ppb8 bus 9
pci9: no spaces enabled!
pchb0 at pci0 dev 24 function 0: PCI configuration registers:
Common header:
0x00: 0x11001022 0x00100000 0x06000000 0x00800000
Vendor ID: 0x1022
Device ID: 0x1100
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000080 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Capability list pointer: 0x80
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Capability register at 0x80
type: 0x08 (LDT)
Device-dependent header:
0x40: 0x00010101 0x00010101 0x00010101 0x00010101
0x50: 0x00010101 0x00010101 0x00010101 0x00010101
0x60: 0x00010000 0x000000e4 0x0f00c820 0x0000000c
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x21010008 0x11110020 0x80750622 0x00000002
0x90: 0x01610169 0x00090000 0x00000007 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
vendor 0x1022 product 0x1100 (host bridge) at ? dev 24 function 0 (intrswiz 0,
intrpin 0, i/o off, mem off, no quirks)
pchb0: vendor 0x1022 product 0x1100 (rev. 0x00)
pchb1 at pci0 dev 24 function 1: PCI configuration registers:
Common header:
0x00: 0x11011022 0x00000000 0x06000000 0x00800000
Vendor ID: 0x1022
Device ID: 0x1101
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0000
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Device-dependent header:
0x40: 0x00000003 0x011f0000 0x00000000 0x00000001
0x50: 0x00000000 0x00000002 0x00000000 0x00000003
0x60: 0x00000000 0x00000004 0x00000000 0x00000005
0x70: 0x00000000 0x00000006 0x00000000 0x00000007
0x80: 0x00000a03 0x00000b00 0x00000000 0x00000000
0x90: 0x00e00003 0x00efff00 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00f40003 0x00fe0200
0xb0: 0x00f00003 0x00f09f80 0x00000000 0x00000000
0xc0: 0x00008013 0x0000f000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x09000003 0x00000000 0x00000000 0x00000000
0xf0: 0xe0002001 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
vendor 0x1022 product 0x1101 (host bridge) at ? dev 24 function 1 (intrswiz 0,
intrpin 0, i/o off, mem off, no quirks)
pchb1: vendor 0x1022 product 0x1101 (rev. 0x00)
pchb2 at pci0 dev 24 function 2: PCI configuration registers:
Common header:
0x00: 0x11021022 0x00000000 0x06000000 0x00800000
Vendor ID: 0x1022
Device ID: 0x1102
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0000
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Device-dependent header:
0x40: 0x00000001 0x00000201 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00f83de0 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000046 0x00000000
0x80: 0x00000005 0x00000000 0x0c7cf224 0x00231320
0x90: 0x00010810 0x7410805b 0x80000024 0x00202520
0xa0: 0x0c0002e9 0x00000000 0x00000000 0x00000000
0xb0: 0x74d88dd0 0x00000025 0xa4209eeb 0x053eba81
0xc0: 0x00020000 0x00000000 0x00000000 0x00000000
0xd0: 0x00a02a83 0x42204554 0x69408861 0xa89032cc
0xe0: 0x00110090 0xa413e757 0x1880c461 0x90c62245
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
vendor 0x1022 product 0x1102 (host bridge) at ? dev 24 function 2 (intrswiz 0,
intrpin 0, i/o off, mem off, no quirks)
pchb2: vendor 0x1022 product 0x1102 (rev. 0x00)
amdtemp0 at pci0 dev 24 function 3: PCI configuration registers:
Common header:
0x00: 0x11031022 0x00100000 0x06000000 0x00800000
Vendor ID: 0x1022
Device ID: 0x1103
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x000000f0 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Capability list pointer: 0xf0
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Capability register at 0xf0
type: 0x0f (Secure Device)
Device-dependent header:
0x40: 0x00000100 0x0a100044 0x00000000 0x00000000
0x50: 0x00428680 0x00000000 0x00000000 0x31050000
0x60: 0x000000d1 0x00000000 0x00000040 0x00000000
0x70: 0x51020111 0x50008011 0x08003800 0x0000222a
0x80: 0x23070000 0x21132113 0x00000000 0x00000000
0x90: 0x00000000 0x00003e34 0x00040000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x000da701 0x00800000 0x00252525
0xe0: 0x00000000 0x00641920 0x00001719 0x00000000
0xf0: 0x0010000f 0x00000000 0x00000000 0x00040f33
Don't know how to pretty-print device-dependent header.
vendor 0x1022 product 0x1103 (host bridge) at ? dev 24 function 3 (intrswiz 0,
intrpin 0, i/o off, mem off, no quirks): AMD CPU Temperature Sensors (K8: core
rev JH-F3, socket AM2)
isa0 at pcib0
pckbc0 at isa0 port 0x60-0x64
pckbd0 at pckbc0 (kbd slot)
pckbc0: using irq 1 for kbd slot
wskbd0 at pckbd0: console keyboard, using wsdisplay0
itesio0 at isa0 port 0x2e-0x2f: iTE IT8716F Super I/O (rev 0)
itesio0: Hardware Monitor registers at 0x290
itesio0: Watchdog Timer present
fwohci0: BUS reset
fwohci0: node_id=0xc800ffc0, gen=1, CYCLEMASTER mode
ieee1394if0: 1 nodes, maxhop <= 0, cable IRM = 0 (me)
ieee1394if0: bus manager 0 (me)
timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
fd0 at fdc0 drive 0: 1.44MB, 80 cyl, 2 head, 18 sec
fd1 at fdc0 drive 1: density unknown
azalia0: codec[0]: Analog Devices AD1988B (rev. 2.0), HDA rev. 1.0
audio0 at azalia0: full duplex, independent
uhub0 at usb0: vendor 0x10de OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub0: 10 ports with 10 removable, self powered
uhub1 at usb1: vendor 0x10de EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
uhub1: 10 ports with 10 removable, self powered
viaide0 port 0: device present, speed: 1.5Gb/s
viaide0 port 1: device present, speed: 3.0Gb/s
ehci0: handing over low speed device on port 2 to ohci0
uhidev0 at uhub0 port 2 configuration 1 interface 0
uhidev0: Justcom Technology USB KVM Switch, rev 1.10/1.00, addr 2, iclass 3/1
ukbd0 at uhidev0: 8 modifier keys, 6 key codes
wskbd1 at ukbd0 mux 1
wskbd1: connecting to wsdisplay0
uhidev1 at uhub0 port 2 configuration 1 interface 1atapibus0 at atabus2: 2
targets
uhidev1: Justcom Technology USB KVM Switch, rev 1.10/1.00, addr 2, iclass 3/1
ums0 at uhidev1: 5 buttons and Z dir.
wsmouse0 at ums0 mux 0
st0 at atapibus0 drive 0: <Seagate STT3401A, hp0atxa, 310B> tape removable
st0: quirks apply, drive empty
st0: 32-bit data port
st0: drive supports PIO mode 3
cd0 at atapibus0 drive 1: <LITE-ON DVDRW SHW-160P6S, , PS08> cdrom removable
cd0: 32-bit data port
cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 4 (Ultra/66)
st0(viaide1:0:0): using PIO mode 3
cd0(viaide1:0:1): using PIO mode 4, Ultra-DMA mode 4 (Ultra/66) (using DMA)
wd0 at atabus0 drive 0: <Maxtor 6L300S0>
wd0: drive supports 16-sector PIO transfers, LBA48 addressing
wd0: 279 GB, 581463 cyl, 16 head, 63 sec, 512 bytes/sect x 586114704 sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
wd0(viaide0:0:0): using PIO mode 4, Ultra-DMA mode 6 (Ultra/133) (using DMA)
wd1 at atabus1 drive 0: <Maxtor 7H500F0>
wd1: drive supports 16-sector PIO transfers, LBA48 addressing
wd1: 465 GB, 969021 cyl, 16 head, 63 sec, 512 bytes/sect x 976773168 sectors
wd1: 32-bit data port
wd1: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
wd1(viaide0:1:0): using PIO mode 4, Ultra-DMA mode 6 (Ultra/133) (using DMA)
pad0: outputs: 44100Hz, 16-bit, stereo
audio2 at pad0: half duplex
boot device: wd0
root on wd0a dumps on wd0b
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