Re: msk(4) require to sync status buffer

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

kiyohara%kk.iij4u.or.jp@localhost wrote:

> > > I think that the processing of the status buffer of msk(4) is strange.
> > > It doesn't do at interrupt handling at all though it does pre-read-sync
> > > only first.  I think that this cannot read a correct value with like CPU
> > > of writeback cache (not PC/AT).
> > 
> > Would something like this be responsible for msk0 not working 
> > correctly after a cold boot?  E.g. requiring a boot to Windows, 
> > configuration of the nic, and then warm-boot to NetBSD, in order to 
> > get the card to function properly?
> 
> My KURO-BOX/PRO don't work msk(4).  It CPU is ARM Feroceon for KURO-BOX/PRO
> with write-back cache.

I guess more strict bus_dmamap_sync(9) calls are required:
---
Index: if_msk.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_msk.c,v
retrieving revision 1.16
diff -u -r1.16 if_msk.c
--- if_msk.c    7 Feb 2008 01:21:56 -0000       1.16
+++ if_msk.c    22 Feb 2008 16:30:40 -0000
@@ -1745,6 +1745,8 @@
                    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 
                cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons];
+               MSK_CDTXSYNC(sc_if, cons, 1,
+                   BUS_DMASYNC_PREREAD);
                sk_ctl = cur_tx->sk_ctl;
 #ifdef MSK_DEBUG
                if (mskdebug >= 2)
@@ -1844,6 +1846,7 @@
        MSK_CDSTSYNC(sc, sc->sk_status_idx,
            BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
        cur_st = &sc->sk_status_ring[sc->sk_status_idx];
+       MSK_CDSTSYNC(sc, sc->sk_status_idx, BUS_DMASYNC_PREREAD);
 
        while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) {
                cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN;
@@ -1877,6 +1880,8 @@
                MSK_CDSTSYNC(sc, sc->sk_status_idx,
                    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
                cur_st = &sc->sk_status_ring[sc->sk_status_idx];
+               MSK_CDSTSYNC(sc, sc->sk_status_idx,
+                   BUS_DMASYNC_PREREAD);
        }
 
        if (status & SK_Y2_IMR_BMU) {

---

but passing BUS_DMA_COHERENT to bus_dmamem_map(9) for
DMA descriptor memory will also work.
---
Izumi Tsutsui