Subject: sdpmem(4) reporting DDR2 speed/type incorrectly
To: None <current-users@netbsd.org>
From: Juan RP <juan@xtrarom.org>
List: current-users
Date: 09/18/2007 02:45:36
Hi,

the spdmem(4) driver reports DDR2 memory speed and type incorrectly;
d_clk shouldn't be multiplied by 4, rather by 2 like DDR.

Also I changed it to report 667 and not 666, not sure what to
do about other types... what do you think about this patch?

Now the information is correct on my system:

spdmem0 at iic0 addr 0x50
spdmem0: DDR2 SDRAM memory, no parity or ECC, 1024MB, 800MHz, PC6400
spdmem0: 14 rows, 10 cols, 2 ranks, 4 banks/chip, 2.50ns cycle time
spdmem0: voltage SSTL 1.8V, refresh time 7.8us (self-refreshing)
spdmem1 at iic0 addr 0x51
spdmem1: DDR2 SDRAM memory, no parity or ECC, 1024MB, 667MHz, PC5300
spdmem1: 14 rows, 10 cols, 2 ranks, 4 banks/chip, 3.00ns cycle time
spdmem1: voltage SSTL 1.8V, refresh time 7.8us (self-refreshing)

previously this reported:

spdmem0 at iic0 addr 0x50
spdmem0: DDR2 SDRAM memory, no parity or ECC, 1024MB, 1600MHz, PC12800
spdmem0: 14 rows, 10 cols, 2 ranks, 4 banks/chip, 2.50ns cycle time
spdmem0: voltage SSTL 1.8V, refresh time 7.8us (self-refreshing)
spdmem1 at iic0 addr 0x51
spdmem1: DDR2 SDRAM memory, no parity or ECC, 1024MB, 1333MHz, PC10700
spdmem1: 14 rows, 10 cols, 2 ranks, 4 banks/chip, 3.00ns cycle time
spdmem1: voltage SSTL 1.8V, refresh time 7.8us (self-refreshing)

Index: spdmem.c
===================================================================
RCS file: /cvsroot/src/sys/dev/i2c/spdmem.c,v
retrieving revision 1.2
diff -b -u -p -r1.2 spdmem.c
--- spdmem.c	9 Sep 2007 13:48:14 -0000	1.2
+++ spdmem.c	18 Sep 2007 00:39:57 -0000
@@ -284,7 +284,7 @@ spdmem_attach(struct device *parent, str
 		d_clk = 100 * 1000;
 		if (s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM) {
 			/* DDR2 uses quad-pumped clock */
-			d_clk *= 4;
+			d_clk *= 2;
 			bits = s->sm_ddr2.ddr2_datawidth;
 			if ((s->sm_config & 0x03) != 0)
 				bits -= 8;
@@ -308,6 +308,8 @@ spdmem_attach(struct device *parent, str
 				bits -= 8;
 		}
 		d_clk /= cycle_time;
+		if (d_clk == 666)
+			d_clk++;
 		p_clk = d_clk * bits / 8;
 		if ((p_clk % 100) >= 50)
 			p_clk += 50;

-- 
Juan Romero Pardines	- The NetBSD Project
http://plog.xtrarom.org	- NetBSD/pkgsrc news in Spanish