cpu0 at mainbus0 apid 0: (boot processor)
cpu0: VIA C7 Esther (686-class), 799.98 MHz, id 0x6a9
cpu0: features a7d9bbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features a7d9bbff<PGE,CMOV,PAT,MPC,NOX,MMXX,MMX>
cpu0: features a7d9bbff<FXSR,SSE,SSE2,LONG,3DNOW>
cpu0: features2 181<SSE3,EST,TM2>
cpu0: padlock features 3fcc<RNG,AES,AES/CTR,SHA1/SHA256,RSA>
cpu0: "VIA Esther processor 1000MHz"
cpu0: I-cache 64 KB 64B/line 4-way, D-cache 64 KB 64B/line 4-way
cpu0: L2 cache 128 KB 64B/line 10-way
cpu0: ITLB 128 4 KB entries 8-way
cpu0: DTLB 128 4 KB entries 8-way
cpu0: using thermal monitor 2
cpu0: Enhanced SpeedStep (1004 mV) 800 MHz
cpu0: unknown Enhanced SpeedStep CPU.
est_init_main: bus_clock = 10000
est_init_main: idlo = 0x810
est_init_main: lo   956 mV,  800 MHz
est_init_main: raw   16   ,    8
est_init_main: idhi = 0xa13
est_init_main: hi  1004 mV, 1000 MHz
est_init_main: raw   19   ,   10
est_init_main: cur  = 0x813
est_init_main: fake entry 0: 1004 mV, 1000 MHz  MSR*100 mV = 1000 freq = 1900
est_init_main: fake entry 1:  988 mV,  900 MHz  MSR*100 mV =  900 freq = 1751
est_init_main: fake entry 2:  972 mV,  800 MHz  MSR*100 mV =  800 freq = 1602
cpu0: Enhanced SpeedStep frequencies available (MHz): 1000 900 800
cpu0: calibrating local timer
cpu0: apic clock running at 99 MHz
cpu0: 4 page colors

This CPU have 3 freqs available: 1000, 900 and 800 MHz
this CPU have 4 voltages available; 1004, 988, 972 and 956 mV

My opinion is, Fake table should be as follows:
entry0 1000 MHz, 1004 mV
entry1  900 MHz,  988 or 972 mV (lower is better)
entry1  800 MHz,  956 mV

But it is just my opinion and I may be wrong

Thanks a lot

Heron Gallegos
Saltillo Coahuila Mexico