Subject: Re: promise sata TX2Plus not configured
To: None <current-users@NetBSD.org>
From: Lukas Diduch <lukasdi@gmx.de>
List: current-users
Date: 03/03/2005 00:03:15
> Hi,
> 
> i've installed a (probably newer model of) a Promise SATA TX2Plus
> controller
> on a u60/sparc64. The system does not recognize the device. (maybe because
> of the fancy id ?)
> 
> dmesg :
Promise Technology product 0x3d75 (miscellaneous mass storage, revision
0x02) at pci0 dev 2 function 0 not configured
psycho1 at mainbus0 addr 0xfffc6000

here's a pcictl dump of the device :

PCI configuration registers:
  Common header:
    0x00: 0x3d75105a 0x02300007 0x01800002 0x00002040

    Vendor Name: Promise Technology (0x105a)
    Device ID: 0x3d75
    Command register: 0x0007
      I/O space accesses: on
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
    Status register: 0x0230
      Capability List support: on
      66 MHz capable: on
      User Definable Features (UDF) support: off
      Fast back-to-back capable: off
      Data parity error detected: off
      DEVSEL timing: medium (0x1)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: mass storage (0x01)
    Subclass Name: miscellaneous (0x80)
    Interface: 0x00
    Revision ID: 0x02
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x20
    Cache Line Size: 0x40

  Type 0 ("normal" device) header:
    0x10: 0x00001801 0x00000000 0x00001c01 0x00110000
    0x20: 0x00120000 0x00000000 0x00000000 0x3d75105a
    0x30: 0x00140000 0x00000060 0x00000000 0x1204010e

    Base address register at 0x10
      type: i/o
      base: 0x00001800, not sized
    Base address register at 0x14
      not implemented(?)
    Base address register at 0x18
      type: i/o
      base: 0x00001c00, not sized
    Base address register at 0x1c
      type: 32-bit nonprefetchable memory
      base: 0x00110000, not sized
    Base address register at 0x20
      type: 32-bit nonprefetchable memory
      base: 0x00120000, not sized
    Base address register at 0x24
      not implemented(?)
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x105a
    Subsystem ID: 0x3d75
    Expansion ROM Base Address: 0x00140000
    Capability list pointer: 0x60
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x12
    Minimum Grant: 0x04
    Interrupt pin: 0x01 (pin A)
    Interrupt line: 0x0e

  Capability register at 0x60
    type: 0x01 (Power Management, rev. 1.0)

  Device-dependent header:
    0x40: 0x00010000 0x00000000 0x00000000 0x00000000
    0x50: 0x00000000 0x00000000 0x00000000 0x00000000
    0x60: 0x02220001 0x00000000 0x00000000 0x00000000
    0x70: 0x00000000 0x00000000 0x00000000 0x00000000
    0x80: 0x00000000 0x00000000 0x00000000 0x00000000
    0x90: 0x00000000 0x00000000 0x00000000 0x00000000
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x04000000 0x0003ffff 0x00000000 0x00000000

would be great to get this one working.

Best regards,
Lukas Diduch

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