Subject: Re: gcc/egcs problem with shifts on i386
To: None <cwood@ichips.intel.com, smd@sean.ebone.net>
From: Sean Doran <smd@sean.ebone.net>
List: current-users
Date: 08/18/1999 13:35:12
| for IA32 ;-) we mask off the lower 5 bits of the shift count and shift by
| this much (so i guess it's mod 32, more or less).  it also means that
| specifying a shift count of 32 will not shift the number at all.  this is
| apparently allowed by the C spec.  oh well...

I get the same result on a SUNW/SPARCstation-LX/TMS390S10.

: cesium.clock.org-MHRC ; ./shift l 0x7fffffff 32
shl 0x7fffffff, 0x20 -> 0x7fffffff
: cesium.clock.org-MHRC ; ./shift l 0x7fffffff 31
shl 0x7fffffff, 0x1f -> 0x80000000
: cesium.clock.org-MHRC ; ./shift r 0x7fffffff 31
shr 0x7fffffff, 0x1f -> 0x0
: cesium.clock.org-MHRC ; ./shift r 0x7fffffff 32
shr 0x7fffffff, 0x20 -> 0x7fffffff

> this only appears to occur on i386

Oops. -:)

Interestingly:

: cesium.clock.org-MHRC ; ./shift r 0x7fffffff 33
shr 0x7fffffff, 0x21 -> 0x3fffffff
: cesium.clock.org-MHRC ; ./shift r 0x7fffffff 34
shr 0x7fffffff, 0x22 -> 0x1fffffff
: cesium.clock.org-MHRC ; ./shift r 0x7fffffff 35
shr 0x7fffffff, 0x23 -> 0xfffffff
: cesium.clock.org-MHRC ; ./shift r 0x7fffffff 62
shr 0x7fffffff, 0x3e -> 0x1
: cesium.clock.org-MHRC ; ./shift r 0x7fffffff 63
shr 0x7fffffff, 0x3f -> 0x0
: cesium.clock.org-MHRC ; ./shift r 0x7fffffff 64
shr 0x7fffffff, 0x40 -> 0x7fffffff

	Sean.