In message <v03110700b08fc1cbd023@[198.68.110.2]>, "Erik E. Fair" writes:
>I got the following today, which hints at a work-around with unacceptable
>performance loss: turning off the L1 cache.

Hrm.  I just noticed that the referenced SCO document specifically
mentions Pentium Pro and Pentium II, but it still seems to imply
that a microcode upgrade should be possible for the P5 for this
particular problem.  Anyone have any other information?