Chris G Demetriou <Chris_G_Demetriou@ux2.sp.cs.cmu.edu> writes:

> 
> To quote the PCI Local Bus Specification (Revision 2.0), page 160:
> 
> "Base registers that map into I/O space are always 32 bits with bit 0
> hardwired to a 1, bit 1 is reserved and must return 0 on reads, and
> the other bits are used to map the device into I/O space (see Figure
> 6-6)."  [ the ... interesting use of parallelism is theirs -- cgd ]
> Earlier in the spec, it says that devices must decode all 32 address
> lines.

It does not specifically say that the device must allow the top bits
to be *changed*, however; figuring out the size by setting all the
bits to 1 and checking to see which ones change is merely a
recommendation.  There is at least one set of cards (BusLogic PCI SCSI
cards) with the top 16 bits hard-wired to 0.  The previous definition
caused this to be mapped incorrectly.