I don't  know if this is the right place to ask this or not, but:


I'm trying to redo the pmax SCC driver (which is essentially the
same as the  Alpha driver)  to use a x1 clock divider.  My aim
here is to use speeds higher than 57600 bps, like  115200.

The pmax (and Alpha) scc driver has a comment that says

/*
 * BRG formula is:
 *				ClockFrequency
 *	BRGconstant = 	---------------------------  -  2
 *			2 * BaudRate * ClockDivider
 *
 * Speed selections with Pclk=7.3728Mhz, clock x16
 */

which seemed in agreement  with the data book last time I checked.
However, when I use rates for a x1  clockdivider, I get lots of
framing errors reported.  (Maybe half the lines I get have all or
most chars with framing errors.)  The rates I compute for 230kps
are the same as the ones quoted in the DEC  Functional Spec for
the 5000/240, so I don't think I've made any obvious mistakes.

I can think of three possible causes for this bug:

	1)  the z8530 just doesn't work reliably with a x1 clock divider;
	    I should just give up :).
	2)  The z8530 can work reliably  with a x1 clock divider, but
	    I'm not frobbing the chip registers in the right order.
	3)  The clock on my motherboard is  marginal wrt the specified
	    rate.

I have no experience with problems like this.  (I've hacked drivers
for z8350 chips on macs, which did run accurately at higher rates, so
I *hop* (1) is not the case.)  Short of getting a 'scope, I'm not sure
how to eliminate (2) or (3).  If anyone has any advice on programming
this chip, I'd appreciate it.

(Gordon, are you out there somewhere??)

--Jonathan