>Date: Fri, 29 Dec 1995 09:14:53 +1100
  >From: George Michaelson <ggm@connect.com.au>
  
  >had to disable my onboard cache to get NetBSD to run.
  >its a MP5-TRI from PCPartner. triton chipset.
  >
  >I have jumper options to control:
  >
  >	L1 cache protocol (write back (default) or write through)
  
  Try setting this one to write-through, and see if that helps.

Works fine now. Many many thanks!

  Write-back caching will fail in the presence of bus masters other than
  the CPU unless the motherboard has implemented cache coherency
  properly.  Cache coherency protocols are nontrivial, so they may have
  done it wrongly.

Is this a common mb failing? resolvable by firmware upgrade or innate
in the hardware on the board?

dmesg shows:

NetBSD 1.1 (GGMHOME) #0: Sun Dec  3 21:53:59 EST 1995
    ggm@ggmhome.off.connect.com.au:/usr/src/sys/arch/i386/compile/GGMHOME
CPU: Pentium (GenuineIntel 586-class CPU)
real mem  = 16384000
avail mem = 14045184
using 225 buffers containing 921600 bytes of memory
isa0 (root)
com0 at isa0 port 0x3f8-0x3ff irq 4: ns16550a, working fifo
com1 at isa0 port 0x2f8-0x2ff irq 3: ns16550a, working fifo
lpt0 at isa0 port 0x378-0x37f irq 7
mcd0: timeout in getresult
mcd0: timeout in getresult
mcd0: timeout in getresult
wdc0 at isa0 port 0x1f0-0x1f7 irq 14
wd0 at wdc0 drive 0: 1033MB, 2100 cyl, 16 head, 63 sec, 512 bytes/sec <WDC AC21000H>
wd0: using 16-sector 16-bit pio transfers, lba addressing
ie0: unknown AT&T board type code 15
sb0 at isa0 port 0x220-0x237 irq 7 drq 1: dsp v3.01
npx0 at isa0 port 0xf0-0xff: using exception 16
vt0 at isa0 port 0x60-0x6f irq 1: unknown s3, 80 col, color, 8 scr, mf2-kbd, [R3.32]
fdc0 at isa0 port 0x3f0-0x3f7 irq 6 drq 2
fd0 at fdc0 drive 0: 1.44MB 80 cyl, 2 head, 18 sec
root device eisa not configured
pci0 (root): configuration mode 1
pci0 bus 0 device 0: unknown vendor/product: 0x8086/0x122d (class: bridge, subclass: host, revision: 0x01) not configured
pci0 bus 0 device 7: unknown vendor/product: 0x8086/0x122e (class: bridge, subclass: ISA, revision: 0x02) not configured
pci0 bus 0 device 18: unknown vendor/product: 0x5333/0x8811 (class: display, subclass: VGA, revision: 0x00) not configured
biomask 40c0 netmask 0 ttymask 1a

  
I'd have assumed from my ignorance only the on-mb IDE was bus mastering
if anything was.

  >	L2 cache size (0,256,512 (selected)
  
  Make sure this matches the amount of cache SRAM you have installed;
  but if this setting is incorrect, I don't see how anything would
  work.

It did, it wasn't. I concur.
  
  >Is there a lucid description of whats going on here online anywhere?
  
  Take a University course on high-performance computer architecture.
  I can provide some book titles on the subject, if such are desired.
  
No, frobbing jumpers and hassling experts works fine :-) I understand
cache principles from a 1980 cs degree perspective, but not the specifics
of how this breaks under bus-mastering and broken h/w architecture...

  >compile options to get cache used properly?
  
  There are options for Cyrix 486DLC motherboards, but they won't help
  you--you have a Pentium.

found these after posting. left well alone.

  
  >(behavior was crash on panic during system startup)
  
  Did the kernel print any messages?

Not to hand. if useful I can re-jumper the mb and try again.

modulo "read the book" what do I win by having write-through enabled
over nothing and write-back as choices? My guess is read caching is
identical for both write-* cases, but I loose slightly with a stall
on memory write, and either is better than none. I have no idea what order
of gain I make from re-enabling caching.

-George