Subject: Re: hardware caches and DMA
To: John F. Woods <firstname.lastname@example.org>
From: Bakul Shah <email@example.com>
Date: 04/15/1995 17:11:56
> Since I am one of the many i386 owners afflicted with caches that don't snoop
> DMA cycles, thus requiring me to run without the external cach
Are there *any* DMA snooping caches available in any PC compatibles?
> is a question affecting any reasonable computer. Of course, the architecture-
> independant answer is probably "Hey, the hardware is supposed to just *work*",
> in which case the question becomes toy-computer specific... :-)
You will find many different cache implementations in pretty
much every computer line. Unless you have only coherent
snoopy caches you have to worry about caches.
> Have I just missed it, or does the software
> make no preparations for starting a transfer other than just ticking the
> device itself? If not, is there an obvious place where to add code to warn
> a deficient cache about an impending transfer?
Quick answer: Flush relevant cache lines *before* starting a
mem->IO device DMA. Invalidate relevant cache lines *after*
finishing a IO->mem DMA. In both cases one presumption is
that you leave address range being DMAed to/from alone
during the transfer. Explicit flushing via software is not
required in a write-through or coherent cache. Invalidating
is done in hardware in a coherent cache implementation
(assuming the DMA device also takes part in the coherent
cache protocol). This can get more complicated depending on
the number of cache levels, the type of cache at each level
and what other games are being played.
I haven't looked at NetBSD DMA code but one simple thing to
do is to use, for example, CACHE_FLUSH(addr,len) and
CACHE_INVALIDATE(addr,len) macros at appropriate points
around where DMA is set up or done. These macros then get
expanded (possibly into just white space) in a
processor/cache arch. specific way.