Theo Deraadt writes:
> 
> > Hmm, I wonder if it has to do with the line size of the internal cache on
> > the i486; if the cache uses a 4-word line size, this alignment might assist
> > the instruction fetch unit so that jumps/branches are cache line-aligned.
> > However, I'm not sure what the line size is, so this is just speculation.
> 
> This is correct. I've never noticed a performance difference from
> the alignment in a NetBSD kernel. I'm sure I can come up with places
> where it is beneficial.
> 
> This is entirely because of Intel's stupid cache reload mechanism
> (all other processors load the long you want first, then rotate
> around to fetch the others. Intel loads the first one, then cylces
> through).


Yes, this is called "wrap-around load."

Aligning the branch targets on cache lines also helps on Intel processors since
instructions can be up to 8 or 10 bytes long (which is it?  Don't remember...),
so aligning the target ensures you that you'll get at least one valid 
instruction fetched out of the line before you get another cache miss; if
the target weren't aligned, you run the risk back-to-back cache misses in
the middle of an instruction fetch.

Have mercy on the poor Intel engineers who carry the baggage of variable-
length instructions (and small register sets, and segmented addressing,
and...)


-dwh-
dhess@cs.stanford.edu

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