Subject: Re: Fix for ac97.c
To: David Laight <david@l8s.co.uk>
From: Julio M. Merino Vidal <jmmv@menta.net>
List: tech-kern
Date: 09/09/2003 20:31:56
Hmmm... auvia's reset function is completely empty! I've been looking at
auich's reset function and Linux ALSA drivers and got the following patch.
It enables the reset code and adds a wait probing the card. Does this seem
correct?
Index: auvia.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/auvia.c,v
retrieving revision 1.31
diff -u -r1.31 auvia.c
--- auvia.c 2003/05/03 18:11:32 1.31
+++ auvia.c 2003/09/09 18:25:34
@@ -128,6 +128,7 @@
#define AUVIA_PCICONF_ACSGD 0x00000400 /* SGD enab */
#define AUVIA_PCICONF_ACFM 0x00000200 /* FM enab */
#define AUVIA_PCICONF_ACSB 0x00000100 /* SB enab */
+#define AUVIA_PCICONF_PRIVALID 0x00000001 /* primary codec rdy */
#define AUVIA_PLAY_BASE 0x00
#define AUVIA_RECORD_BASE 0x10
@@ -364,7 +365,7 @@
void
auvia_reset_codec(void *addr)
{
-#ifdef notyet /* XXX seems to make codec become unready... ??? */
+ int i;
struct auvia_softc *sc = addr;
pcireg_t r;
@@ -380,8 +381,11 @@
pci_conf_write(sc->sc_pc, sc->sc_pt, AUVIA_PCICONF_JUNK, r);
delay(200);
- auvia_waitready_codec(sc);
-#endif
+ for (i = 500000; i != 0 && !(pci_conf_read(sc->sc_pc, sc->sc_pt,
+ AUVIA_PCICONF_JUNK) & AUVIA_PCICONF_PRIVALID); i--)
+ DELAY(1);
+ if (i == 0)
+ printf("%s: codec reset timed out\n", sc->sc_dev.dv_xname);
}
Thanks
On Tue, 9 Sep 2003 17:55:40 +0100
David Laight <david@l8s.co.uk> wrote:
> >
> > I overlooked delay() units. Well, have tried with smaller delay values but
> > it keeps failing.
>
> In that case the delay is needed for something else!
>
> > Here are all reset related timings present in the datasheet,
> > in case I got them wrong:
> >
> > RESET Active Low Pulsewidth - Max empty
> > RESER Inactive to BIT_CLK Startup Delay - Max 400,000 ns
> > Setup to RESET Inactive (SYNC, SDATA_OUT) - Min 15 ns, Max empty
> > Rising Edge of RESET to Hi-Z Delay - 25 ns
> > RESET Rise Time - 50 ns
>
> My guess is that the device ID (and other config) is being read in from
> a serial EPROM. So that after a hard reset you have to wait long enough
> for that to have been read.
>
> Might be worth looking what the BIT_CLK is used for - if you need it to
> be running the delay is quite long (also check it applies to software
> resets though).
>
> >
> > auvia has a TIMEOUT=50 constant that specifies how many loop iterations
> > should be done waiting for a read. I guess this computer is so fast
> > (XP2600+) that the 50 value is not enough (it's not a delay()).
>
> That is just plain borked - the compiler could even optimse the loop away!
>
>
> David
>
> --
> David Laight: david@l8s.co.uk
--
Julio M. Merino Vidal <jmmv@menta.net>
The NetBSD Project - http://www.NetBSD.org/