>How does your bus_dma changes deal with systems that have DMA
>incoherent cache.  bus_dmamap_sync would seem to require 
>keeping the MI segments around...

Why do you assume that the implementation requires data in exactly the
format of MI segments in order to perform cache invalidation?  It may well
be, for example, that the MI segs are 64bit based where 32bit mappings suit
the implementation fine.  It may be that the implementation really wants to
keep a list of page table entries instead.  You really don't know, nor
should the client of the map care.  If the implementation must keep
something akin to an MI dm_segs array in the dma map, then there is no
space savings *for that implementation* (and no additional cost over what
NetBSD does now either), but the API should not enforce this restriction on
all implementations.

>-- 
>Matt Thomas               Internet:   matt@3am-software.com
>3am Software Foundry      WWW URL:    http://www.3am-software.com/bio/matt/
>Nashua, NH                Disclaimer: I disavow all knowledge of this message

--
Justin