The Chinese Computer Tech. Lab. once (in 2001) finished a CPU design that
is compatable with MIPS cpu with register rename, dynamic pipeline, out of
order execution... It was verified on FPGA with 4KB instruction cache, 4KB
data cahce, 48 entries TLB. The main bus on motherboard runs at 50MHz
and the FPGA runs at 12.5MHz. At 12.5 MHz the integer performance is like
a 25MHz 486 abd the floating point (IEEE745) performance is like a 50MHz
486. Overall performance is 1/6 of a 100MHz MIPS R4000.

Don't know how fast it will run if implemented as a ASIC CPU but you get
the idea how fast the FGPA VAX will probably run. And that was NOT a
single person project.

http://www.ict.ac.cn/xinwen/dt011014_1.htm  (not in English)


On Tue, 26 Feb 2002, Thor Lancelot Simon wrote:

> On Tue, Feb 26, 2002 at 06:13:23PM -0500, Gunther Schadow wrote:
> > Hello, for those of you who are not (or no longer :-) subscribed to the
> > Quasijarus list, you still want to read this. This is Michael Sokolov
> > as we all love him: Passionate and knowledgeable about VAXen, and just
> > that. The project sounds kinda cool, if he delivers I'll want to get it.
> 
> Oh, yeah, sure, if you ignore everything about it that's wildly at odds
> with reality.  Care to tell me how he's going to make his FPGA with his
> new VAX core on it run at anywhere near the clock rates the later VAXen
> ran at?
> 
>