There is very little documentation on the '750 gate arrays. I've read
the uFiche gate array manual with a great lack of satisfaction... 

The arrays are apparently 400 gate NMOS NAND arrays with different 
metalization, so reversing them wouldn't be too tough... Still easier
to implement from the VARM though.

CLint

On Tue, 26 Jun 2001, Lord Isildur wrote:

> Hmm.. I have a 730 that could also be sacrificed (blasphemy!) for 
> analysis. Preferably analysed nondestructively.. :) 
> I would still go for the 750. The fact that it was done in 2901s makes it
> easier i think. There should be less debugging to do and fewer goofups,
> since one could build fewer subunits and debug them more separately- we
> all know what a 2901 shoudl behave like, or if not can find it in our local
> library. The 780 is too big a design, i think, and has too many parts that
> DEC realized (like compatibility mode) were not necessary, and the 750 really
> benefited from this work. 
> 
> Isildur
> 
> On Tue, 26 Jun 2001, Brian Chase wrote:
> 
> > On Tue, 26 Jun 2001, Lord Isildur wrote:
> > 
> > > [...]
> > >
> > > i have some friend shere with access to lots of xilinx and verilog stuff,
> > > it might not be too impractical to try to make a 750 on a chip. I'd go
> > > with the 750 and not the 780, i think there were a lot of advances in
> > > those couple years.
> > 
> > What about the 11/730?  The 11/750 used 2901 bitslice processors which
> > might pose a challenge (???)  I believe the 11/730 is pure TTL.  It's
> > slow, and simpler than the 11/780 (I don't think it had provisions for the
> > PDP-11 compatibility mode).  It's sort of a no-go if no one has any print
> > sets for it, but I believe it'd be easier to implement in VHDL than an
> > 11/780.
> > 
> > -brian.
> > 
> > 
> 
>