PR/49468 CVS commit: src/sys/arch/arm/cortex

["Jared D. McNeill" <jmcneill%netbsd.org@localhost>]

The following reply was made to PR port-evbarm/49468; it has been noted by GNATS.

From: "Jared D. McNeill" <jmcneill%netbsd.org@localhost>
To: gnats-bugs%gnats.NetBSD.org@localhost
Cc: 
Subject: PR/49468 CVS commit: src/sys/arch/arm/cortex
Date: Wed, 7 Feb 2018 20:42:17 +0000

 Module Name:	src
 Committed By:	jmcneill
 Date:		Wed Feb  7 20:42:17 UTC 2018
 
 Modified Files:
 	src/sys/arch/arm/cortex: gic.c
 
 Log Message:
 PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC
 
 The priority level is changed by writing to GICC_PMR with interrupts
 disabled. However, interrupts are enabled/disabled downstream of the GICC
 at the CPU. When raising priority level, there is a window between the time
 that interrupts are disabled and the GICC_PMR register is written. If an
 interrupt occurs at a previously allowed priority before GICC_PMR is
 changed, the CPU will receive the signal when interrupts are re-enabled.
 At this time, GICC_PMR is now the new priority level, so reads of
 GICC_IAR will report a spurious IRQ.
 
 Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
 there is at least one pending IRQ.
 
 
 To generate a diff of this commit:
 cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/cortex/gic.c
 
 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.