Subject: port-i386/3953: The if_fxp driver could be updated
To: None <gnats-bugs@gnats.netbsd.org>
From: Havard Eidnes <he@vader.runit.sintef.no>
List: netbsd-bugs
Date: 08/07/1997 13:27:43
>Number:         3953
>Category:       port-i386
>Synopsis:       The if_fxp driver could be updated
>Confidential:   no
>Severity:       non-critical
>Priority:       medium
>Responsible:    gnats-admin (GNATS administrator)
>State:          open
>Class:          change-request
>Submitter-Id:   net
>Arrival-Date:   Thu Aug  7 04:35:01 1997
>Last-Modified:
>Originator:     Havard Eidnes
>Organization:
	SINTEF RUNIT
>Release:        NetBSD-current 3 Jul 1997
>Environment:
System: NetBSD vader.runit.sintef.no 1.2G NetBSD 1.2G (VADER) #3: Thu Jul 3 20:04:47 MEST 1997 he@vader.runit.sintef.no:/usr/src/sys/arch/i386/compile/VADER i386


>Description:
	The if_fxp driver could be updated with the changes done
	in the FreeBSD driver since it was imported to NetBSD.

	(I guess port-i386 being most relevant, although the driver
	living in /sys/dev/pci purports to be MI.)

	My primary motive for updating: on an Intel EtherExpress Pro 100B
	we have we appear to have the 82555 chip (?), causing a message saying
	"unsupported PHY type=7, addr=1" when it's ifconfig'ed.  Nevertheless
	it appeared to work before these changes, but merging the FreeBSD
	changes seemed like the Right Thing to do.

	The driver has been cursorily tested after applying these changes,
	by booting an SSTO floppy and doing some simple ping testing.

>How-To-Repeat:
	Inspect the RCS IDs in FreeBSD and NetBSD for the relevant files.

>Fix:
	Apply this diff in /sys/dev/pci

*** if_fxp.c.old	Thu Jun  5 13:22:55 1997
--- if_fxp.c	Thu Aug  7 12:57:21 1997
***************
*** 30,34 ****
   * SUCH DAMAGE.
   *
!  *	Id: if_fxp.c,v 1.34 1997/04/23 01:44:30 davidg Exp
   */
  
--- 30,34 ----
   * SUCH DAMAGE.
   *
!  *	Id: if_fxp.c,v 1.38 1997/08/02 14:33:10 bde Exp
   */
  
***************
*** 49,64 ****
  #include <net/if.h>
  #include <net/if_dl.h>
- #include <net/if_types.h>
  
  #ifdef INET
  #include <netinet/in.h>
- #include <netinet/in_systm.h>
- #include <netinet/in_var.h>
- #include <netinet/ip.h>
- #endif
- 
- #ifdef IPX
- #include <netipx/ipx.h>
- #include <netipx/ipx_if.h>
  #endif
  
--- 49,55 ----
***************
*** 70,74 ****
  #if NBPFILTER > 0
  #include <net/bpf.h>
- #include <net/bpfdesc.h>
  #endif
  
--- 61,64 ----
***************
*** 109,113 ****
  
  #include <vm/vm.h>		/* for vtophys */
- #include <vm/vm_param.h>	/* for vtophys */
  #include <vm/pmap.h>		/* for vtophys */
  #include <machine/clock.h>	/* for DELAY */
--- 99,102 ----
***************
*** 876,888 ****
  					sc->tx_queued--;
  				}
! 				if (txp->cb_command & FXP_CB_COMMAND_S)
  					break;
  			}
  			sc->cbl_first = txp;
  			/*
! 			 * Clear watchdog timer. It may or may not be set
! 			 * again in fxp_start().
  			 */
- 			ifp->if_timer = 0;
  			if (ifp->if_snd.ifq_head != NULL)
  				fxp_start(ifp);
--- 865,876 ----
  					sc->tx_queued--;
  				}
! 				if (txp == sc->cbl_last)
  					break;
  			}
  			sc->cbl_first = txp;
+ 			ifp->if_timer = 0;
  			/*
! 			 * Try to start more packets transmitting.
  			 */
  			if (ifp->if_snd.ifq_head != NULL)
  				fxp_start(ifp);
***************
*** 1271,1278 ****
  
  	/*
! 	 * Toggle a few bits in the DP83840 PHY.
  	 */
! 	if (sc->phy_primary_device == FXP_PHY_DP83840 ||
! 	     sc->phy_primary_device == FXP_PHY_DP83840A) {
  		fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR,
  		    fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) |
--- 1259,1267 ----
  
  	/*
! 	 * Toggle a few bits in the PHY.
  	 */
! 	switch (sc->phy_primary_device) {
! 	case FXP_PHY_DP83840:
! 	case FXP_PHY_DP83840A:
  		fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR,
  		    fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) |
***************
*** 1280,1283 ****
--- 1269,1274 ----
  		    FXP_DP83840_PCR_F_CONNECT |	/* force link disconnect bypass */
  		    FXP_DP83840_PCR_BIT10);	/* XXX I have no idea */
+ 		/* fall through */
+ 	case FXP_PHY_82555:
  		/*
  		 * If link0 is set, disable auto-negotiation and then:
***************
*** 1292,1313 ****
  
  			flags = (ifp->if_flags & IFF_LINK1) ?
! 			     FXP_DP83840_BMCR_SPEED_100M : 0;
  			flags |= (ifp->if_flags & IFF_LINK2) ?
! 			     FXP_DP83840_BMCR_FULLDUPLEX : 0;
  			fxp_mdi_write(sc, sc->phy_primary_addr,
! 			    FXP_DP83840_BMCR,
  			    (fxp_mdi_read(sc, sc->phy_primary_addr,
! 			    FXP_DP83840_BMCR) &
! 			    ~(FXP_DP83840_BMCR_AUTOEN |
! 			      FXP_DP83840_BMCR_SPEED_100M |
! 			     FXP_DP83840_BMCR_FULLDUPLEX)) | flags);
  		} else {
  			fxp_mdi_write(sc, sc->phy_primary_addr,
! 			    FXP_DP83840_BMCR,
  			    (fxp_mdi_read(sc, sc->phy_primary_addr,
! 			     FXP_DP83840_BMCR) |
! 			    FXP_DP83840_BMCR_AUTOEN));
  		}
! 	} else {
  		printf(FXP_FORMAT
  		    ": warning: unsupported PHY, type = %d, addr = %d\n",
--- 1283,1311 ----
  
  			flags = (ifp->if_flags & IFF_LINK1) ?
! 			     FXP_PHY_BMCR_SPEED_100M : 0;
  			flags |= (ifp->if_flags & IFF_LINK2) ?
! 			     FXP_PHY_BMCR_FULLDUPLEX : 0;
  			fxp_mdi_write(sc, sc->phy_primary_addr,
! 			    FXP_PHY_BMCR,
  			    (fxp_mdi_read(sc, sc->phy_primary_addr,
! 			    FXP_PHY_BMCR) &
! 			    ~(FXP_PHY_BMCR_AUTOEN |
! 			      FXP_PHY_BMCR_SPEED_100M |
! 			     FXP_PHY_BMCR_FULLDUPLEX)) | flags);
  		} else {
  			fxp_mdi_write(sc, sc->phy_primary_addr,
! 			    FXP_PHY_BMCR,
  			    (fxp_mdi_read(sc, sc->phy_primary_addr,
! 			     FXP_PHY_BMCR) |
! 			    FXP_PHY_BMCR_AUTOEN));
  		}
! 		break;
! 	/*
! 	 * The Seeq 80c24 doesn't have a PHY programming interface, so do
! 	 * nothing.
! 	 */
! 	case FXP_PHY_80C24:
! 		break;
! 	default:
  		printf(FXP_FORMAT
  		    ": warning: unsupported PHY, type = %d, addr = %d\n",
*** if_fxpreg.h.old	Thu Jun  5 13:22:55 1997
--- if_fxpreg.h	Thu Aug  7 12:54:03 1997
***************
*** 27,31 ****
   * SUCH DAMAGE.
   *
!  *	Id: if_fxpreg.h,v 1.8 1997/03/21 08:00:13 davidg Exp
   */
  
--- 27,31 ----
   * SUCH DAMAGE.
   *
!  *	Id: if_fxpreg.h,v 1.9 1997/06/13 22:34:52 davidg Exp
   */
  
***************
*** 302,314 ****
  #define FXP_PHY_80C240		5
  #define FXP_PHY_80C24		6
  #define FXP_PHY_DP83840A	10
  
  /*
!  * DP84830 PHY, BMCR Basic Mode Control Register
   */
! #define FXP_DP83840_BMCR		0x0
! #define FXP_DP83840_BMCR_FULLDUPLEX	0x0100
! #define FXP_DP83840_BMCR_AUTOEN		0x1000
! #define FXP_DP83840_BMCR_SPEED_100M	0x2000
  
  /*
--- 302,315 ----
  #define FXP_PHY_80C240		5
  #define FXP_PHY_80C24		6
+ #define FXP_PHY_82555		7
  #define FXP_PHY_DP83840A	10
  
  /*
!  * PHY BMCR Basic Mode Control Register
   */
! #define FXP_PHY_BMCR			0x0
! #define FXP_PHY_BMCR_FULLDUPLEX		0x0100
! #define FXP_PHY_BMCR_AUTOEN		0x1000
! #define FXP_PHY_BMCR_SPEED_100M		0x2000
  
  /*
>Audit-Trail:
>Unformatted: