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Re: Memory alignment

On Fri, Dec 04, 2009 at 10:14:52AM -0500, Greg Troxel wrote:
> [...]
> I don't think the CPU architecture itself guarantees anything about
> cache line size.

For x86 at last it doesn't. There are CPUs with 32 bytes cache lines,
and some with 64 bytes. Even worse, Xeons have 64 bytes lines but do
adjacent lines prefetches, so I suspect for this kind of optimisation,
the right value to consider is 128 bytes.

Manuel Bouyer <>
     NetBSD: 26 ans d'experience feront toujours la difference

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